Method and apparatus for fast modulation in synchronous CDMA
communications
    41.
    发明授权
    Method and apparatus for fast modulation in synchronous CDMA communications 失效
    同步CDMA通信中快速调制的方法和装置

    公开(公告)号:US5864548A

    公开(公告)日:1999-01-26

    申请号:US779263

    申请日:1997-01-06

    Applicant: Hui Liu

    Inventor: Hui Liu

    CPC classification number: H04B1/707

    Abstract: A system and method for modulating synchronous CDMA (S-CDMA) signals in antenna array wireless system. By taking advantage of the symmetric property of Walsh code words utilized in S-CDMA perform modulation of signals intended for a plurality of users. The system includes a Fast Hadamard Transform (FHT) Processor that realizes baseband operations including spreading and digital combining in one step. In addition to significant reduction in computations and storage over prior methods, the invention also provides substantial advantages in hardware implementation. While the exemplary embodiment is described in the context of antenna array CDMA systems, the disclosed techniques have general applications in CDMA systems with arbitrary symbol values.

    Abstract translation: 一种在天线阵列无线系统中调制同步CDMA(S-CDMA)信号的系统和方法。 通过利用在S-CDMA中使用的沃尔什码字的对称性来执行针对多个用户的信号的调制。 该系统包括一个快速Hadamard变换(FHT)处理器,实现基带操作,包括一步一步的扩展和数字组合。 除了相对于现有方法的计算和存储的显着减少之外,本发明还在硬件实现方面提供了显着的优点。 虽然在天线阵列CDMA系统的上下文中描述了示例性实施例,但是所公开的技术在具有任意符号值的CDMA系统中具有一般应用。

    Selectable PA bias temperature compensation circuitry
    46.
    发明授权
    Selectable PA bias temperature compensation circuitry 有权
    可选PA偏置温度补偿电路

    公开(公告)号:US08983407B2

    公开(公告)日:2015-03-17

    申请号:US13288318

    申请日:2011-11-03

    Abstract: Radio frequency (RF) power amplifier (PA) circuitry, which transmits RF signals is disclosed. The RF PA circuitry includes a final stage, a final stage current digital-to-analog converter (IDAC), and a final stage temperature compensation circuit. A final stage current reference circuit may provide an uncompensated final stage reference current to the final stage temperature compensation circuit, which receives and temperature compensates the uncompensated final stage reference current to provide a final stage reference current. The final stage IDAC uses the final stage reference current in a digital-to-analog conversion to provide a final stage bias signal to bias the final stage. The temperature compensation provided by the final stage temperature compensation circuit is selectable.

    Abstract translation: 公开了发射RF信号的射频(RF)功率放大器(PA)电路。 RF PA电路包括最后级,最后一级电流数模转换器(IDAC)和最终级温度补偿电路。 最终级电流参考电路可以向最终级温度补偿电路提供未补偿的最终级参考电流,其接收和温度补偿未补偿的最终级参考电流以提供最终级参考电流。 最终阶段IDAC在数模转换中使用最后阶段参考电流,以提供最终阶段偏置信号来偏向最后阶段。 由最终级温度补偿电路提供的温度补偿是可选择的。

    Efficient broadcasting via random linear packet combining
    47.
    发明授权
    Efficient broadcasting via random linear packet combining 有权
    通过随机线性分组组合进行有效的广播

    公开(公告)号:US08953612B2

    公开(公告)日:2015-02-10

    申请号:US13414235

    申请日:2012-03-07

    CPC classification number: H04L1/0076 H04H20/42 H04L1/0057 H04L69/22 H04W4/06

    Abstract: Embodiments of systems and methods for efficient broadcasting via random linear packet combining are described. A plurality of data packets are received from a data source according to embodiments. The plurality of data packets is divided into a plurality of data blocks, and bits associated with the plurality of data blocks are multiplied by a set of coefficients to generate a plurality of product values. An encoded data packet having a plurality of encoded data blocks may also be generated by linearly combining the plurality of product values for respective data blocks of each of the plurality of data packets into corresponding encoded data blocks of the encoded data packet. Because each encoded data packet includes information about a complete set of data packets, rather than just a subset, less broadcast redundancy may be required.

    Abstract translation: 描述了通过随机线性分组组合进行有效广播的系统和方法的实施例。 根据实施例,从数据源接收多个数据分组。 多个数据分组被分成多个数据块,并且与多个数据块相关联的比特乘以一系列系数以产生多个乘积值。 也可以通过将多个数据分组中的每一个的各个数据块的多个乘积值线性地组合成编码数据分组的相应的编码数据块来生成具有多个编码数据块的编码数据分组。 因为每个编码的数据分组包括关于完整的一组数据分组的信息,而不仅仅是一个子集,所以可能需要较少的广播冗余。

    Skewed partial column input/output floorplan
    48.
    发明授权
    Skewed partial column input/output floorplan 有权
    偏斜的部分列输入/输出平面图

    公开(公告)号:US08791573B1

    公开(公告)日:2014-07-29

    申请号:US13601894

    申请日:2012-08-31

    Abstract: Techniques and mechanisms for providing embedded Input/Output (IO) blocks in a floor plan of a semiconductor device are provided, where the embedded IO blocks constitute partial columns (i.e., they do not extend from the bottom through to the top of the semiconductor device). In some embodiments, the partial column IO banks are skewed away from one another. In some embodiments, the partial column IO banks are located away from the center of the semiconductor device. Techniques and mechanisms for implementing symmetrical package routing using skewed partial column IO banks are also provided.

    Abstract translation: 提供了在半导体器件的平面图中提供嵌入式输入/输出(IO)块的技术和机制,其中嵌入式IO块构成部分列(即,它们不从半导体器件的底部到顶部延伸) )。 在一些实施例中,部分列IO组彼此偏斜。 在一些实施例中,部分列IO组位于远离半导体器件的中心的位置。 还提供了使用偏斜部分列IO库来实现对称封装路由的技术和机制。

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