公开(公告)号：US20210193510A1

公开(公告)日：2021-06-24

申请号：US17119802

申请日：2020-12-11

Applicant: IMEC vzw

Inventor： Boon Teik Chan ,  Efrain Altamirano Sanchez ,  Geert Mannaert

IPC: H01L21/762 ,  H01L21/8234

Abstract: According to an aspect of the disclosed technology, there is provided a method comprising: providing a substrate, the substrate supporting an STI-layer and a set of fin structures, each fin structure comprising an upper portion protruding above the STI-layer, forming a spacer layer over the upper portions of the set of fin structures and the STI-layer, forming a sacrificial layer over the spacer layer, the sacrificial layer at least partially embedding the upper portions of the fin structures, partially etching back the sacrificial layer to expose spacer layer portions above upper surfaces of the upper portions of the set of fin structures, and etching the spacer layer and exposing at least the upper surfaces of the upper portions of the set of fin structures, while the sacrificial layer at least partially masks spacer layer portions above the STI-layer.

公开(公告)号：US20210126108A1

公开(公告)日：2021-04-29

申请号：US17083125

申请日：2020-10-28

Applicant: IMEC vzw

Inventor： Boon Teik Chan ,  Dunja Radisic ,  Steven Demuynck ,  Efrain Altamirano Sanchez ,  Soon Aik Chew

IPC: H01L29/66 ,  H01L21/768

Abstract: The disclosed technology is related to a method that includes the formation of contact vias for contacting gate electrodes and source (S) or drain (D) electrodes of nano-sized semiconductor transistors formed on a semiconductor wafer. The electrodes are mutually parallel and provided with dielectric gate and S/D plugs on top of the electrodes, and the mutually parallel electrode/plug assemblies are separated by dielectric spacers. The formation of the vias takes place by two separate self-aligned etch processes, the Vint-A etch for forming one or more vias towards one or more S/D electrodes and the Vint-G etch for forming one or more vias towards one or more gate electrodes. According to the disclosed technology, a conformal layer is deposited on the wafer after the first self-aligned etch process, wherein the conformal layer is resistant to the second self-aligned etch process. The conformal layer thereby protects the first contact via during the second self-aligned etch.

公开(公告)号：US10825682B2

公开(公告)日：2020-11-03

申请号：US15258838

申请日：2016-09-07

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Vasile Paraschiv ,  Efrain Altamirano Sanchez ,  Zheng Tao

IPC: H01L21/3065 ,  H01L21/308 ,  H01L21/306 ,  H01L21/02 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  B82Y40/00 ,  B82Y10/00 ,  H01L21/265 ,  H01L21/28

Abstract: A method for producing a pillar structure in a semiconductor layer, the method including providing a structure including, on a main surface, a semiconductor layer. A patterned hard mask layer stack is provided on the semiconductor layer that includes a first layer in contact with the semiconductor layer and a second layer overlying and in contact with the first layer. The semiconductor layer is etched using the patterned hard mask layer stack as a mask. The etching includes subjecting the structure to a first plasma thereby removing a first part of the semiconductor layer and at least a part of the second layer while preserving the first layer thereby, producing a first part of the pillar structure, thereafter; and subjecting the structure to a second plasma thereby removing a second part of the semiconductor layer thereby, producing a second part of the pillar structure.

公开(公告)号：US10790382B2

公开(公告)日：2020-09-29

申请号：US15845300

申请日：2017-12-18

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Silvia Armini ,  Elisabeth Camerotto ,  Zheng Tao

IPC: H01L29/66 ,  H01L29/775 ,  H01L29/10 ,  H01L29/786 ,  H01L29/423 ,  H01L29/06 ,  H01L29/78 ,  B82Y10/00

Abstract: A method for forming horizontal nanowires, the method comprising providing a substrate comprising a dielectric layer and a fin structure comprising a portion protruding from the dielectric layer, the protruding portion being partially un-masked and comprising a multi-layer stack consisting of a layer of a first material stacked alternately and repeatedly with a layer of a second material and forming horizontal nanowires done by performing a cycle comprising removing selectively the first material up to the moment that a horizontal nanowire of the second material becomes suspended over a remaining portion of the partially un-masked protruding portion, forming a sacrificial layer on the remaining portion, while leaving the suspended horizontal nanowire uncovered, providing, selectively, a cladding layer on the suspended horizontal nanowire, and thereafter removing the sacrificial layer. The horizontal nanowires become suspended starting from the top and the cladding layer is removed, after the bottom horizontal nanowire becomes suspended.

公开(公告)号：US20190355619A1

公开(公告)日：2019-11-21

申请号：US16412923

申请日：2019-05-15

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Efrain Altamirano Sanchez

IPC: H01L21/768 ,  H01L21/311

Abstract: A method for forming a cavity in a semiconductor structure and an intermediate structure is provided. The method includes: (a) providing a semiconductor structure comprising: (i) a semiconductor substrate; (ii) a set of line structures on the semiconductor substrate, each line structure having a top surface and sidewalls, the line structures being separated by trenches therebetween, and (iii) an oxygen-containing dielectric material at least partially filling the trenches in-between the line structures, wherein the top surface of at least one of the line structures is at least partially exposed, and wherein the exposed part of the top surface is composed of an oxygen-free dielectric material; (b) forming a layer of TaSix selectively onto the oxygen-free dielectric material with respect to the oxygen-containing dielectric material (c) forming the cavity by selectively removing at least a portion of the oxygen-containing dielectric material with respect to the TaSix.

公开(公告)号：US10303048B2

公开(公告)日：2019-05-28

申请号：US15433397

申请日：2017-02-15

Applicant: IMEC VZW ,  KATHOLIEKE UNIVERSITEIT LEUVEN, KU LEUVEN R&D

Inventor： Boon Teik Chan ,  Arjun Singh ,  Safak Sayan

IPC: B32B7/00 ,  G03F7/00 ,  H01L21/033 ,  H01L21/027

Abstract: The present disclosure relates to a patterned structure, the structure comprising: i) a substrate, ii) a first layer on top of the substrate, comprising a filler material and a guiding material, wherein at least a top surface of the first layer comprises one or more zones of filler material and one or more zones of guiding material, and iii) a second layer on top of the first layer comprising a pattern of a first material, the pattern being either aligned or anti-aligned with the underlying one or more zones of guiding material; wherein the first material comprises a metal or a ceramic material and wherein the guiding material and the filler material either both comprise or both do not comprise the metal or ceramic material.

公开(公告)号：US20190057859A1

公开(公告)日：2019-02-21

申请号：US16103370

申请日：2018-08-14

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Jean-Francois de Marneffe

IPC: H01L21/027 ,  H01L21/033

Abstract: In one aspect, the present disclosure relates to a method. The method includes providing a substrate having a patterned layer thereon, the patterned layer including an opening that exposes the substrate. The method also includes selectively infiltrating the patterned layer with a metal or ceramic material, thereby reducing a dimension of the opening. The opening exposes the substrate after the dimension of the opening is reduced.

公开(公告)号：US10128371B2

公开(公告)日：2018-11-13

申请号：US15292778

申请日：2016-10-13

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Clement Merckling ,  Zheng Tao

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/20 ,  H01L29/66 ,  H01L29/786

Abstract: A method for forming a semiconductor device is disclosed. The method includes providing a semiconductor substrate. The method also includes epitaxially growing on the semiconductor substrate a first part of a III-V semiconductor nanostructure. The method further includes covering the first part of the III-V semiconductor nanostructure with a layer of a first material. Additionally, the method includes removing a top portion of the layer of the first material. Still further, the method includes epitaxially growing on the first part of the III-V semiconductor nanostructure a second part of the III-V semiconductor nanostructure. The method additionally includes covering the second part of the III-V semiconductor nanostructure with a layer of a second material. The second material is different from the first material. Even further, the method includes removing a top portion of the layer of the second material.

公开(公告)号：US20180043283A1

公开(公告)日：2018-02-15

申请号：US15674438

申请日：2017-08-10

Applicant: IMEC VZW

Inventor： Zheng Tao ,  Boon Teik Chan ,  XiuMei Xu ,  Khashayar Babaei Gavan ,  Efrain Altamirano Sanchez

IPC: B01D15/10 ,  B01D53/04

CPC classification number: B01D15/10 ,  B01D53/0407 ,  B01D63/14 ,  B01L3/502753 ,  B01L2300/0896 ,  B81B2201/058 ,  B81B2201/10 ,  B81B2203/0315 ,  B81B2203/0338 ,  B81B2203/0346 ,  B81B2203/0384 ,  B81C1/00119 ,  C12M1/123 ,  C12M33/14

Abstract: A method for producing a structure including, on a main surface of a substrate, at least one elongated cavity having openings at opposing ends. The method includes providing a substrate having a main surface. On the main surface, a first pair of features are formed that protrude perpendicularly from the main surface. The features have elongated sidewalls and a top surface, are parallel to one another, are separated by a gap having a width s1 and a bottom area, and have a width w1 and a height h1. At least the main surface of the substrate and the first pair of features are brought in contact with a liquid, suitable for making a contact angle of less than 90° with the material of the elongated sidewalls and subsequently the substrate is dried.

公开(公告)号：US20170179281A1

公开(公告)日：2017-06-22

申请号：US15292778

申请日：2016-10-13

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Clement Merckling ,  Zheng Tao

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/10 ,  H01L21/02 ,  H01L29/20

CPC classification number: H01L29/7827 ,  H01L21/02538 ,  H01L21/02603 ,  H01L29/0676 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/20 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/78642

Abstract: A method for forming a semiconductor device is disclosed. The method includes providing a semiconductor substrate. The method also includes epitaxially growing on the semiconductor substrate a first part of a III-V semiconductor nanostructure. The method further includes covering the first part of the III-V semiconductor nanostructure with a layer of a first material. Additionally, the method includes removing a top portion of the layer of the first material. Still further, the method include epitaxially growing on the first part of the III-V semiconductor nanostructure a second part of the III-V semiconductor nanostructure. The method additionally includes covering the second part of the III-V semiconductor nanostructure with a layer of a second material. The second material is different from the first material. Even further, the method includes removing a top portion of the layer of the second material.