公开(公告)号：US09721898B2

公开(公告)日：2017-08-01

申请号：US15285454

申请日：2016-10-04

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Don Nelson ,  M. Clair Webb ,  Kimin Jun ,  Il-Seok Son

IPC: H01L23/535 ,  H01L21/20 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L21/74 ,  H01L23/50 ,  H01L27/12

CPC classification number: H01L23/535 ,  H01L21/2007 ,  H01L21/743 ,  H01L23/50 ,  H01L23/522 ,  H01L23/5286 ,  H01L24/18 ,  H01L27/1207

Abstract: Methods of forming microelectronic interconnect under device structures are described. Those methods and structures may include forming a device layer in a first substrate, forming at least one routing layer in a second substrate, and then coupling the first substrate with the second substrate, wherein the first substrate is bonded to the second substrate.

公开(公告)号：US20170025355A1

公开(公告)日：2017-01-26

申请号：US15285454

申请日：2016-10-04

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Don Nelson ,  M. Clair Webb ,  Kimin Jun ,  II-Seok Son

IPC: H01L23/535 ,  H01L23/50 ,  H01L23/528 ,  H01L27/12 ,  H01L21/74

CPC classification number: H01L23/535 ,  H01L21/2007 ,  H01L21/743 ,  H01L23/50 ,  H01L23/522 ,  H01L23/5286 ,  H01L24/18 ,  H01L27/1207

Abstract: Methods of forming microelectronic interconnect under device structures are described. Those methods and structures may include forming a device layer in a first substrate, forming at least one routing layer in a second substrate, and then coupling the first substrate with the second substrate, wherein the first substrate is bonded to the second substrate.

Abstract translation: 描述了在器件结构下形成微电子互连的方法。 这些方法和结构可以包括在第一衬底中形成器件层，在第二衬底中形成至少一个布线层，然后将第一衬底与第二衬底耦合，其中第一衬底与第二衬底结合。

公开(公告)号：US09548320B2

公开(公告)日：2017-01-17

申请号：US14930171

申请日：2015-11-02

Applicant: INTEL CORPORATION

Inventor： Alejandro X. Levander ,  Kimin Jun

IPC: H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L27/12 ,  H01L21/762 ,  H01L21/265 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/311 ,  H01L29/06 ,  H01L29/26

CPC classification number: H01L27/1207 ,  H01L21/02002 ,  H01L21/02521 ,  H01L21/02634 ,  H01L21/02642 ,  H01L21/02647 ,  H01L21/265 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/76251 ,  H01L21/76254 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/26

Abstract: Techniques are disclosed for heteroepitaxial growth of a layer of lattice-mismatched semiconductor material on an initial substrate, and transfer of a defect-free portion of that layer to a handle wafer or other suitable substrate for integration. In accordance with some embodiments, transfer may result in the presence of island-like oxide structures on the handle wafer/substrate, each having a defect-free island of the lattice-mismatched semiconductor material embedded within its upper surface. Each defect-free semiconductor island may have one or more crystalline faceted edges and, with its accompanying oxide structure, may provide a planar surface for integration. In some cases, a layer of a second, different semiconductor material may be heteroepitaxially grown over the handle wafer/substrate to fill areas around the transferred islands. In some other cases, the handle wafer/substrate itself may be homoepitaxially grown to fill areas around the transferred islands.

Abstract translation: 公开了在初始衬底上的晶格失配的半导体材料层的异质外延生长的技术，以及将该层的无缺陷部分转移到处理晶片或其它合适的衬底以进行集成。 根据一些实施例，转移可能导致在手柄晶片/衬底上存在岛状氧化物结构，每个具有嵌入其上表面内的晶格失配的半导体材料的无缺陷岛。 每个无缺陷的半导体岛可以具有一个或多个晶面的边缘，并且随着其伴随的氧化物结构可提供用于集成的平坦表面。 在一些情况下，第二不同的半导体材料的层可以在手柄晶片/衬底上异质外延生长以填充转移的岛周围的区域。 在一些其它情况下，处理晶片/衬底本身可以被同侧外延生长以填充转移的岛周围的区域。

公开(公告)号：US09177967B2

公开(公告)日：2015-11-03

申请号：US14139954

申请日：2013-12-24

Applicant: Intel Corporation

Inventor： Alejandro X. Levander ,  Kimin Jun

IPC: H01L27/00 ,  H01L21/00 ,  H01L27/12 ,  H01L21/762 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L27/1207 ,  H01L21/02002 ,  H01L21/02521 ,  H01L21/02634 ,  H01L21/02642 ,  H01L21/02647 ,  H01L21/265 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/76251 ,  H01L21/76254 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/26

Abstract: Techniques are disclosed for heteroepitaxial growth of a layer of lattice-mismatched semiconductor material on an initial substrate, and transfer of a defect-free portion of that layer to a handle wafer or other suitable substrate for integration. In accordance with some embodiments, transfer may result in the presence of island-like oxide structures on the handle wafer/substrate, each having a defect-free island of the lattice-mismatched semiconductor material embedded within its upper surface. Each defect-free semiconductor island may have one or more crystalline faceted edges and, with its accompanying oxide structure, may provide a planar surface for integration. In some cases, a layer of a second, different semiconductor material may be heteroepitaxially grown over the handle wafer/substrate to fill areas around the transferred islands. In some other cases, the handle wafer/substrate itself may be homoepitaxially grown to fill areas around the transferred islands.

Abstract translation: 公开了在初始衬底上的晶格失配的半导体材料层的异质外延生长的技术，以及将该层的无缺陷部分转移到处理晶片或其它合适的衬底以进行集成。 根据一些实施例，转移可能导致在手柄晶片/衬底上存在岛状氧化物结构，每个具有嵌入其上表面内的晶格失配的半导体材料的无缺陷岛。 每个无缺陷的半导体岛可以具有一个或多个晶面的边缘，并且随着其伴随的氧化物结构可提供用于集成的平坦表面。 在一些情况下，第二不同的半导体材料的层可以在手柄晶片/衬底上异质外延生长以填充转移的岛周围的区域。 在一些其它情况下，处理晶片/衬底本身可以被同侧外延生长以填充转移的岛周围的区域。

公开(公告)号：US20250112208A1

公开(公告)日：2025-04-03

申请号：US18478686

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Thomas L. Sounart ,  Feras Eid ,  Kimin Jun ,  Tushar Kanti Talukdar ,  Andrey Vyatskikh ,  Johanna Swan ,  Shawna M. Liff

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/15

Abstract: Methods of selectively transferring portions of layers between substrates, and devices and systems formed using the same, are disclosed herein. In one embodiment, a microelectronic assembly includes a solid glass layer, a plurality of mesa structures on a surface of the glass layer, and an integrated circuit (IC) component on each respective mesa structure. The mesa structures have similar footprints as the IC components, and may be formed on or integrated with the glass layer.

公开(公告)号：US20250112200A1

公开(公告)日：2025-04-03

申请号：US18374559

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Kimin Jun ,  Feras Eid ,  Thomas Sounart ,  Yi Shi ,  Shawna Liff ,  Johanna Swan ,  Michael Baker ,  Bhaskar Jyoti Krishnatreya ,  Chien-An Chen

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

Abstract: A surface of an integrated circuit (IC) die structure and a substrate to which the IC die structure is to be bonded include biphilic regions suitable for liquid droplet formation and droplet-based fine alignment of the IC die structure to the substrate. To ensure warpage of the IC die structure does not interfere with droplet-based fine alignment process, an IC die structure of greater thickness is aligned to the substrate and thickness of the IC die structure subsequently reduced. In some embodiments, a back side of the IC die structure is polished back post attachment. In some alternative embodiments, the IC die structure includes sacrificial die-level carrier is removed after fine alignment and/or bonding.

公开(公告)号：US20250112199A1

公开(公告)日：2025-04-03

申请号：US18374520

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Thomas Sounart ,  Feras Eid ,  Adel Elsherbini ,  Yi Shi ,  Michael Baker ,  Kimin Jun ,  Wenhao Li

IPC: H01L23/00 ,  H01L25/065

Abstract: Hybrid bonded multi-level die stacks, related apparatuses, systems, and methods of fabrication are disclosed. First-level integrated circuit (IC) dies and a base substrate each include hybrid bonding regions surrounded by hydrophobic structures. The hybrid bonding regions are brought together with a liquid droplet therebetween, and capillary forces cause the IC die to self-align. A hybrid bond is formed by evaporating the droplet followed by anneal. Hybrid bonding regions of second-level IC dies are similarly bonded to hybrid bonding regions on backsides of the first-level IC dies. This is repeated for any number of subsequent levels of IC dies. IC structures including the bonded IC dies and portions of the base substrate are segmented and assembled.

公开(公告)号：US20250112155A1

公开(公告)日：2025-04-03

申请号：US18374532

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Kimin Jun ,  Scott Clendenning ,  Feras Eid ,  Robert Jordan ,  Wenhao Li ,  Jiun-Ruey Chen ,  Tayseer Mahdi ,  Carlos Felipe Bedoya Arroyave ,  Shashi Bhushan Sinha ,  Anandi Roy ,  Tristan Tronic ,  Dominique Adams ,  William Brezinski ,  Richard Vreeland ,  Thomas Sounart ,  Brian Barley ,  Jeffery Bielefeld

IPC: H01L23/532 ,  H01L21/48 ,  H01L23/498 ,  H01L23/528

Abstract: Hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. One or both of an integrated circuit (IC) die hybrid bonding region and a base substrate hybrid bonding region are surrounded by a protective layer and hydrophobic structures on the protective layer. The protective layer is formed prior to pre-bond processing to protect the hybrid bonding region during plasma activation, clean test, high temperature processing, or the like. Immediately prior to bonding, the hydrophobic structures are selectively applied to the protective layer. The hybrid bonding regions are brought together with a liquid droplet therebetween, and capillary forces cause the IC die to self-align. A hybrid bond is formed by evaporating the droplet and a subsequent anneal. The hydrophobic structures contain the liquid droplet for alignment during bonding.

公开(公告)号：US12266570B2

公开(公告)日：2025-04-01

申请号：US17133065

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Kimin Jun ,  Souvik Ghosh ,  Willy Rachmady ,  Ashish Agrawal ,  Siddharth Chouksey ,  Jessica Torres ,  Jack Kavalieros ,  Matthew Metz ,  Ryan Keech ,  Koustav Ganguly ,  Anand Murthy

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/522 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H10B61/00 ,  H10B63/00

Abstract: An integrated circuit interconnect structure includes a metallization level above a first device level. The metallization level includes an interconnect structure coupled to the device structure, a conductive cap including an alloy of a metal of the interconnect structure and either silicon or germanium on an uppermost surface of the interconnect structure. A second device level above the conductive cap includes a transistor coupled with the conductive cap. The transistor includes a channel layer including a semiconductor material, where at least one sidewall of the conductive cap is co-planar with a sidewall of the channel layer. The transistor further includes a gate on a first portion of the channel layer, where the gate is between a source region and a drain region, where one of the source or the drain region is in contact with the conductive cap.

公开(公告)号：US20250105046A1

公开(公告)日：2025-03-27

申请号：US18473905

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Thomas L. Sounart ,  Feras Eid ,  Tushar Kanti Talukdar ,  Brandon M. Rawlings ,  Andrey Vyatskikh ,  Carlos Bedoya Arroyave ,  Kimin Jun ,  Shawna M. Liff ,  Grant M. Kloster ,  Richard F. Vreeland ,  William P. Brezinski ,  Johanna Swan

IPC: H01L21/683 ,  H01L23/00 ,  H01L25/065

Abstract: Methods of selectively transferring portions of layers between substrates, and devices and systems formed using the same, are disclosed herein. In one embodiment, a first substrate with a layer of integrated circuit (IC) components is received, and a second substrate with one or more adhesive areas is received. The first substrate is partially bonded to the second substrate, such that a subset of IC components on the first substrate are bonded to the adhesive areas on the second substrate. The first substrate is then separated from the second substrate, and the subset of IC components bonded to the second substrate are separated from the first substrate and remain on the second substrate.