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    DIE-TO-DIE INTERCONNECT PROTOCOL LAYER
    41.
    发明申请
    DIE-TO-DIE INTERCONNECT PROTOCOL LAYER 有权

    公开(公告)号：US20220327084A1

    公开(公告)日：2022-10-13

    申请号：US17853502

    申请日：2022-06-29

    Applicant: Intel Corporation

    Inventor： Debendra Das Sharma ,  Swadesh Choudhary ,  Narasimha Lanka ,  Lakshmipriya Seshan ,  Gerald Pasdast ,  Zuoguo Wu

    IPC: G06F13/42 ,  G06F13/40 ,  G06F11/10

    Abstract: Protocol layer logic in a protocol stack receives an indication that a particular mode is to be utilized on a die-to-die (D2D) link connecting a first device to a second device. The protocol layer logic generates data to be sent on the D2D link to adapt the particular data format to a flit format defined for use on the D2D link in the particular mode, the flit format comprises providing a set of reserved fields to be completed by an adapter block positioned between the protocol circuitry and a physical layer block. The data in the flit format is sent to the data to the adapter block to prepare the data for transmission over the D2D link.

    Multichip package link error detection
    42.
    发明授权
    Multichip package link error detection 有权

    公开(公告)号：US11307928B2

    公开(公告)日：2022-04-19

    申请号：US16938842

    申请日：2020-07-24

    Applicant: Intel Corporation

    Inventor： Venkatraman Iyer ,  Robert G. Blankenship ,  Mahesh Wagh ,  Zuoguo Wu

    IPC: G06F11/10 ,  H03M13/00 ,  H04L9/40 ,  H04L1/00 ,  H04L1/20 ,  G06F13/16 ,  H04L1/16

    Abstract: First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.

    Extending multichip package link off package
    44.
    发明授权
    Extending multichip package link off package 有权

    公开(公告)号：US11113225B2

    公开(公告)日：2021-09-07

    申请号：US16946109

    申请日：2020-06-05

    Applicant: Intel Corporation

    Inventor： Debendra Das Sharma ,  Zuoguo Wu ,  Mahesh Wagh ,  Mohiuddin M. Mazumder ,  Venkatraman Iyer ,  Jeff C. Morriss

    IPC: G06F13/366 ,  G06F13/40 ,  H01L25/065 ,  G06F13/42 ,  H01L23/538

    Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.

    CHARACTERIZATION OF TRANSMISSION MEDIA
    47.
    发明申请
    CHARACTERIZATION OF TRANSMISSION MEDIA 审中-公开

    公开(公告)号：US20190293708A1

    公开(公告)日：2019-09-26

    申请号：US16302555

    申请日：2016-05-17

    Applicant: Intel Corporation

    Inventor： Mayue Xie ,  Chengqing Hu ,  Jong-Ru Guo ,  Zuoguo Wu ,  Deepak Goyal

    IPC: G01R31/28 ,  G01R31/11

    Abstract: Disclosed herein are systems and methods for the characterization of transmission media, among other embodiments. For example, a system for characterizing a transmission medium may include: a waveform generator to generate an initial input waveform; waveform pre-processing circuitry to process the initial waveform to generate a processed input waveform for provision to the transmission medium, wherein the processed input waveform has a maximum amplitude greater than a maximum amplitude of the initial input waveform; and waveform output circuitry to display or store data representative of an initial output waveform, wherein the initial output waveform is output from the transmission medium as a reflection or transmission of the processed input waveform.

    VALID LANE TRAINING
    48.
    发明申请
    VALID LANE TRAINING 审中-公开

    公开(公告)号：US20190238179A1

    公开(公告)日：2019-08-01

    申请号：US15761408

    申请日：2015-09-26

    Applicant: Intel Corporation

    Inventor： Venkatraman Iyer ,  Lip Khoon Teh ,  Mahesh Wagh ,  Zuoguo Wu ,  Azydee Hamid ,  Gerald S. Pasdast

    IPC: H04B3/40 ,  H04L25/03 ,  G06F13/20

    CPC classification number: H04B3/40 ,  G06F13/20 ,  G06F13/40 ,  H04L25/03006 ,  H04L2025/0377

    Abstract: One or more link training signals are received, including instances of a link training pattern, on a plurality of lanes of a physical link that includes at least one valid lane and a plurality of data lanes. The plurality of lanes are trained together using the link training signals to synchronize sampling of the valid lane with sampling of the plurality of data lanes. An active link state is entered and a valid signal received on the valid lane during the active link state. The valid signal includes a signal held at a value for a defined first duration and indicates that data is to be received on the plurality of data lanes in a second defined duration subsequent to the first duration. The data is to be received, during the active link state, on the plurality of data lanes during the second defined duration.

    Apparatus and method for classifying and locating electrical faults in circuitry
    49.
    发明授权
    Apparatus and method for classifying and locating electrical faults in circuitry 有权

    公开(公告)号：US10088518B1

    公开(公告)日：2018-10-02

    申请号：US15474674

    申请日：2017-03-30

    Applicant: Intel Corporation

    Inventor： Mayue Xie ,  Zhiguo Qian ,  Jong-Ru Guo ,  Zhichao Zhang ,  Zuoguo Wu

    IPC: G01R31/08 ,  G01R31/28

    Abstract: A die with a transmission circuit, a reception circuit, and a comparison circuit can be provided. The transmission circuit can be configured to transmit a first signal through a first channel at a first transmission rate and a first transmission amplitude. The reception circuit can be in communication with the transmission circuit through the first channel. The reception circuit can receive a second signal at a first reception rate and at a first reception amplitude. The comparison circuit can be in communication with the transmission circuit and the reception circuit. The comparison circuit can be configured to: determine a first rate error value, determine a first amplitude error value, compare the first rate error value with a rate threshold to determine a first rate error occurrence, and compare the first amplitude error value with an amplitude threshold to determine a first amplitude error occurrence.

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