公开(公告)号：US20150085408A1

公开(公告)日：2015-03-26

申请号：US14037768

申请日：2013-09-26

Applicant: International Business Machines Corporation

Inventor： John J. Ellis-Monaghan ,  Alain Loiseau

IPC: H02H9/04

CPC classification number: H02H9/046

Abstract: An integrated circuit is disclosed, including a circuit with a first type of FET having a first breakdown voltage (VBD), resulting from a first set of design and manufacturing process parameters and having VBD tracking characteristics resulting from a second set of design and manufacturing process parameters. The IC may include a trigger device circuit a having a trigger FET that may generate, in response to the supply voltage exceeding a specified maximum, a signal on a trigger device output, causing a clamping device to couple the supply voltage node to the ground, to reduce the supply voltage. The trigger FET may be of a second type having a second VBD less than the first VBD, resulting from modifications to the first set of design and manufacturing process parameters, and VBD tracking characteristics resulting from the second set of design and manufacturing process parameters.

Abstract translation: 公开了一种集成电路，包括具有第一类型FET的电路，其具有由第一组设计和制造工艺参数产生的第一击穿电压（VBD），并具有由第二组设计和制造过程产生的VBD跟踪特性 参数。 IC可以包括具有触发FET的触发装置电路a，其可以响应于超过指定最大值的电源电压而产生触发装置输出上的信号，使得钳位装置将电源电压节点耦合到地， 降低电源电压。 触发FET可以是具有小于第一VBD的第二VBD的第二类型，这是由第一组设计和制造工艺参数的修改以及由第二组设计和制造工艺参数产生的VBD跟踪特性导致的。

公开(公告)号：US20150014771A1

公开(公告)日：2015-01-15

申请号：US13939353

申请日：2013-07-11

Applicant: International Business Machines Corporation

Inventor： David G. Brochu, JR. ,  John J. Ellis-Monaghan ,  Michael J. Hauser ,  Jeffrey B. Johnson ,  Xuefeng Liu

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7833 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0653 ,  H01L29/0821 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/66681 ,  H01L29/732 ,  H01L29/7816

Abstract: A semiconductor device comprising dual L-shaped drift regions in a lateral diffused metal oxide semiconductor (LDMOS) and a method of making the same. The LDMOS in the semiconductor device comprises a trench isolation region or a deep trench encapsulated by a liner, a first L-shaped drift region, and a second L-shaped drift region. The LDMOS comprising the dual L-shape drift regions is integrated with silicon-germanium (SiGe) technology. The LDMOS comprising the dual L-shape drift regions furnishes a much higher voltage drop in a lateral direction within a much shorter distance from a drain region than the traditional LDMOS does.

Abstract translation: 在横向扩散金属氧化物半导体（LDMOS）中包括双L型漂移区域的半导体器件及其制造方法。 半导体器件中的LDMOS包括由衬垫封装的沟槽隔离区域或深沟槽，第一L形漂移区域和第二L形漂移区域。 包括双L形漂移区的LDMOS与硅 - 锗（SiGe）技术集成。 包括双L形漂移区域的LDMOS在距离漏极区域比传统的LDMOS短得多的距离内在横向上提供高得多的电压降。

公开(公告)号：US08809155B2

公开(公告)日：2014-08-19

申请号：US13644918

申请日：2012-10-04

Applicant: International Business Machines Corporation

Inventor： John J. Ellis-Monaghan ,  Michael J. Hauser ,  Zhong-Xiang He ,  Xuefeng Liu ,  Richard A. Phelps ,  Robert M. Rassel ,  Anthony K. Stamper

IPC: H01L21/336

CPC classification number: H01L29/93 ,  H01L27/0688 ,  H01L27/0808

Abstract: Device structures, design structures, and fabrication methods for a varactor. The device structure includes a first electrode formed on a dielectric layer, and a semiconductor body formed on the first electrode. The semiconductor body is comprised of a silicon-containing semiconductor material in an amorphous state or a polycrystalline state. The device structure further includes an electrode insulator formed on the semiconductor body and a second electrode formed on the electrode insulator.

Abstract translation: 变容二极管的器件结构，设计结构和制造方法。 器件结构包括形成在电介质层上的第一电极和形成在第一电极上的半导体本体。 半导体本体由非晶态或多晶态的含硅半导体材料构成。 器件结构还包括形成在半导体主体上的电极绝缘体和形成在电极绝缘体上的第二电极。

公开(公告)号：US20140225166A1

公开(公告)日：2014-08-14

申请号：US13767024

申请日：2013-02-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Derrick Liu

IPC: G01N27/414 ,  H01L29/66

CPC classification number: G01N27/414 ,  G01N27/4145 ,  G01N27/4148 ,  H01L29/66477

Abstract: Device structures, fabrication methods, and design structures for a biological and chemical sensor used to detect a property of a substance. The device structure includes a drain and a source of a field effect transistor formed at a frontside of a substrate. A sensing layer is formed at a backside of the substrate. The sensing layer is configured to receive the substance.

Abstract translation: 用于检测物质性质的生物和化学传感器的装置结构，制造方法和设计结构。 器件结构包括形成在衬底前侧的场效应晶体管的漏极和源极。 感光层形成在基板的背面。 感测层被配置为接收物质。

公开(公告)号：US20140004687A1

公开(公告)日：2014-01-02

申请号：US14018814

申请日：2013-09-05

Applicant: International Business Machines Corporation

Inventor： Alan B. Botula ,  John J. Ellis-Monaghan ,  Alvin J. Joseph ,  Max G. Levy ,  Richard A. Phelps ,  James A. Slinkman ,  Randy L. Wolf

IPC: H01L21/02

CPC classification number: H01L21/02488 ,  H01L21/2652 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78603

Abstract: Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure.

Abstract translation: 公开了在半导体衬底上具有绝缘体层并且器件层位于绝缘体层上的半导体结构。 衬底掺杂有相对低剂量的具有给定导电类型的掺杂剂，使得其具有相对高的电阻率。 此外，与绝缘体层紧密相邻的半导体衬底的一部分可掺杂略高的相同掺杂剂剂量，具有相同导电类型的不同掺杂剂或其组合。 可选地，在该相同部分内形成微腔，以便平衡由于掺杂增加导致的电导率的增加，同时具有相应的电阻率增加。 增加半导体衬底 - 绝缘体层界面处的掺杂剂浓度会提高任何结果的寄生电容器的阈值电压（Vt），从而降低谐波行为。 本文还公开了用于形成这种半导体结构的方法的实施例。

公开(公告)号：US11409046B2

公开(公告)日：2022-08-09

申请号：US16739418

申请日：2020-01-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Yoba Amoah ,  Brennan J. Brown ,  John J. Ellis-Monaghan ,  Ashleigh R. Kreider

IPC: G02B6/12 ,  G02B6/26 ,  G02B6/32 ,  G02B6/34 ,  G02B6/30 ,  G02B6/10 ,  G02B6/293 ,  G02B6/42 ,  G02B6/35

Abstract: A wafer structure includes a diffractive lens disposed on a backside of a wafer and coupled to a front side waveguide, the diffractive lens being configured to receive light and focus the light to the front side waveguide.

公开(公告)号：US09627575B2

公开(公告)日：2017-04-18

申请号：US14483584

申请日：2014-09-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Kirk D. Peterson

IPC: H01L31/0232 ,  H01L21/00 ,  H01L31/18 ,  H01L31/103 ,  G02B6/12 ,  H01L31/028 ,  H01P1/17 ,  H01L31/02 ,  H01P3/16

CPC classification number: H01L31/1872 ,  G02B6/12 ,  G02B6/12004 ,  H01L31/02005 ,  H01L31/02327 ,  H01L31/028 ,  H01L31/103 ,  H01L31/1808 ,  H01L31/1864 ,  H01L2223/6627 ,  H01P1/172 ,  H01P3/16 ,  Y02E10/50

Abstract: Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material.

公开(公告)号：US09588293B2

公开(公告)日：2017-03-07

申请号：US14749806

申请日：2015-06-25

Applicant: International Business Machines Corporation

Inventor： John J. Ellis-Monaghan ,  Brendan S. Harris ,  Vibhor Jain ,  Thomas Kessler ,  Yves T. Ngu ,  Sebastian T. Ventrone

IPC: G02B6/12 ,  G02B6/125 ,  G02B6/122 ,  G02B6/35 ,  G02B6/28 ,  B81B7/02

CPC classification number: G02B6/125 ,  B81B7/02 ,  B81B2201/045 ,  G02B6/1225 ,  G02B6/2808 ,  G02B6/3502 ,  G02B6/3562 ,  G02B6/357 ,  G02B6/3596 ,  G02B6/3598 ,  G02B2006/12145 ,  G02B2006/1215

Abstract: Various particular embodiments include a primary waveguide including an end section; cantilevered waveguides, each cantilevered waveguide including an end section disposed adjacent the end section of the primary waveguide; and control pins for applying an electrical bias to the cantilevered waveguides to selectively displace the end sections of the cantilevered waveguides away from the end section of the primary waveguide.

Abstract translation: 各种具体实施例包括：包括端部的主波导; 悬臂波导，每个悬臂式波导包括邻近初级波导的端部设置的端部; 以及控制引脚，用于将电偏压施加到悬臂波导，以选择性地使悬臂波导的端部远离主波导的端部。

公开(公告)号：US09240463B2

公开(公告)日：2016-01-19

申请号：US13902245

申请日：2013-05-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： John J. Ellis-Monaghan ,  Theodore J. Letavic ,  Santosh Sharma ,  Yun Shi ,  Michael J. Zierak

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66681 ,  H01L23/60 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/1045 ,  H01L29/404 ,  H01L29/405 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

Abstract: High-voltage LDMOS devices with voltage linearizing field plates and methods of manufacture are disclosed. The method includes forming an array of poly islands and a control gate structure by patterning a poly layer formed over a deep well region and a body of a substrate. The method further includes forming a metal shield in contact with the control gate structure and over the array of poly islands.

Abstract translation: 公开了具有电压线性化场板的高压LDMOS器件和制造方法。 该方法包括通过对在深阱区域和衬底的主体上形成的多晶硅层进行构图来形成多岛阵列和控制栅极结构。 该方法还包括形成与控制栅极结构接触并且在多岛阵列上的金属屏蔽。

公开(公告)号：US20150347667A1

公开(公告)日：2015-12-03

申请号：US14665242

申请日：2015-03-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： John J. Ellis-Monaghan ,  Bertrand Gabillard ,  Philippe Hauviller ,  Michel Rivier

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: Checking the layout integrity includes the steps of receiving inputs defining a plurality of devices for a layout, generating a signature for each device in the layout, when created, from one or more parameters of the device, storing the generated signatures with the layout, receiving the stored layout and signatures, regenerating each signature for each device in the stored layout, and comparing each regenerated signature with the corresponding stored signature.

Abstract translation: 检查布局完整性包括以下步骤：接收定义用于布局的多个设备的输入，当从设备的一个或多个参数创建时，在布局中为每个设备生成签名，存储所生成的签名与布局，接收 存储的布局和签名，对存储的布局中的每个设备重新生成每个签名，并将每个再生的签名与相应的存储的签名进行比较。