公开(公告)号：US20160365411A1

公开(公告)日：2016-12-15

申请号：US14739543

申请日：2015-06-15

Applicant: International Business Machines Corporation ,  Globalfoundries, Inc. ,  STMicroelectronics, Inc.

Inventor： Chun-Chen Yeh ,  Xiuyu Cai ,  Qing Liu ,  Ruilong Xie

IPC: H01L29/06 ,  H01L21/265 ,  H01L29/78 ,  H01L21/3065 ,  H01L29/66

CPC classification number: H01L29/0673 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/3065 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78654 ,  H01L29/78696 ,  H01L2029/7858

Abstract: Embodiments are directed to a method of fabricating a portion of a nanowire field effect transistor (FET). The method includes forming a sacrificial layer and a nanowire layer, removing a sidewall portion of the sacrificial layer and forming a diffusion block in a space that was occupied by the removed sidewall portion of the sacrificial layer. The method further includes forming a source region and a drain region such that the diffusion block is between the sacrificial layer and at least one of the source region and the drain region, and removing the sacrificial layer using a sacrificial layer removal process, wherein the diffusion block prevents the sacrificial layer removal process from also removing portions of at least one of the source region and the drain region.

Abstract translation: 实施例涉及制造纳米线场效应晶体管（FET）的一部分的方法。 该方法包括形成牺牲层和纳米线层，去除牺牲层的侧壁部分，并在牺牲层被去除的侧壁部分占据的空间中形成扩散块。 该方法还包括形成源极区域和漏极区域，使得扩散块在牺牲层与源区域和漏极区域中的至少一个之间，以及使用牺牲层去除工艺去除牺牲层，其中扩散 块防止牺牲层去除过程也去除源区和漏区中的至少一个的部分。

公开(公告)号：US09515180B2

公开(公告)日：2016-12-06

申请号：US14588318

申请日：2014-12-31

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Xiuyu Cai ,  Chun-chen Yeh ,  Ruilong Xie

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/51 ,  H01L21/265 ,  H01L21/266 ,  H01L21/28

CPC classification number: H01L29/7855 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/28141 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/41783 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66484 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7831 ,  H01L29/785

Abstract: A vertical slit transistor includes raised source, drain, and channel regions in a semiconductor substrate. Two gate electrodes are positioned adjacent respective sidewalls of the semiconductor substrate. A dielectric material separates the gate electrodes from the source and drain regions.

Abstract translation: 垂直狭缝晶体管包括半导体衬底中的凸起的源极，漏极和沟道区。 两个栅极位于半导体衬底的相应侧壁附近。 电介质材料将栅电极与源区和漏区分开。

公开(公告)号：US09466722B2

公开(公告)日：2016-10-11

申请号：US14584639

申请日：2014-12-29

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, Inc.

Inventor： Qing Liu ,  Ruilong Xie ,  Xiuyu Cai ,  Chun-chen Yeh

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/08 ,  H01L29/45 ,  H01L21/02 ,  H01L21/8234

CPC classification number: H01L29/7851 ,  H01L21/02181 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795

Abstract: A large area electrical contact for use in integrated circuits features a non-planar, sloped bottom profile. The sloped bottom profile provides a larger electrical contact area, thus reducing the contact resistance, while maintaining a small contact footprint. The sloped bottom profile can be formed by recessing an underlying layer, wherein the bottom profile can be crafted to have a V-shape, U-shape, crescent shape, or other profile shape that includes at least a substantially sloped portion in the vertical direction. In one embodiment, the underlying layer is an epitaxial fin of a FinFET. A method of fabricating the low-resistance electrical contact employs a thin etch stop liner for use as a hard mask. The etch stop liner, e.g., HfO2, prevents erosion of an adjacent gate structure during the formation of the contact.

Abstract translation: 用于集成电路的大面积电接触具有非平面，倾斜的底部轮廓。 倾斜的底部轮廓提供更大的电接触面积，从而降低接触电阻，同时保持小的接触足迹。 倾斜的底部轮廓可以通过凹陷下面的层来形成，其中底部轮廓可以被制造成具有V形，U形，月牙形或其它轮廓形状，其在垂直方向上至少包括基本上倾斜的部分 。 在一个实施例中，下层是FinFET的外延翅片。 制造低电阻电接触的方法采用用作硬掩模的薄蚀刻停止衬垫。 蚀刻停止衬垫，例如HfO 2，防止在形成接触期间相邻栅极结构的侵蚀。

公开(公告)号：US20160293638A1

公开(公告)日：2016-10-06

申请号：US15177715

申请日：2016-06-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc.

Inventor： Bruce Doris ,  Gauri Karve ,  Qing Liu

IPC: H01L27/12 ,  H01L21/02 ,  H01L29/08 ,  H01L29/417 ,  H01L27/088 ,  H01L29/161 ,  H01L29/78 ,  H01L21/8258 ,  H01L21/84 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L27/1211 ,  H01L21/02057 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/8258 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A fin of silicon-germanium material is formed and covered with an epitaxially grown layer of silicon material. A dummy transistor gate is then formed to extend over a channel of the fin. Sidewall spacers are formed on each side of the dummy transistor gate and directly on top of the expitaxial silicon layer. Epitaxially grown raised source and drain regions are formed on each side of the dummy transistor gate adjacent the sidewall spacers. The dummy transistor gate and a portion of the epitaxial silicon layer (underneath said dummy transistor gate) are removed and replaced by a metal gate.

Abstract translation: 形成硅 - 锗材料的翅片并用外延生长的硅材料层覆盖。 然后形成虚拟晶体管栅极以在鳍的沟道上延伸。 侧壁间隔物形成在虚拟晶体管栅极的两侧，并直接在外延硅层的顶部。 外延生长的源极和漏极区域形成在邻近侧壁间隔物的虚拟晶体管栅极的每一侧上。 虚拟晶体管栅极和外延硅层的一部分（在所述虚设晶体管栅极之下）被去除并由金属栅极代替。

公开(公告)号：US20160293494A1

公开(公告)日：2016-10-06

申请号：US15180158

申请日：2016-06-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC. ,  STMICROELECTRONICS, INC.

Inventor： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L21/8238 ,  H01L21/768 ,  H01L21/84

CPC classification number: H01L21/823807 ,  H01L21/76895 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/786 ,  H01L29/78684

Abstract: A method for making a semiconductor device is provided. Raised source and drain regions are formed with a tensile strain-inducing material, after thermal treatment to form source drain extension regions, to thereby preserve the strain-inducing material in desired substitutional states.

公开(公告)号：US09431514B2

公开(公告)日：2016-08-30

申请号：US14577316

申请日：2014-12-19

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Qing Liu ,  Bruce Doris ,  Gauri Karve

IPC: H01L21/335 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L29/423 ,  H01L21/306 ,  H01L21/02

CPC classification number: H01L27/1211 ,  H01L21/02057 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/8258 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A fin of silicon-germanium material is formed and covered with an epitaxially grown layer of silicon material. A dummy transistor gate is then formed to extend over a channel of the fin. Sidewall spacers are formed on each side of the dummy transistor gate and directly on top of the expitaxial silicon layer. Epitaxially grown raised source and drain regions are formed on each side of the dummy transistor gate adjacent the sidewall spacers. The dummy transistor gate and a portion of the epitaxial silicon layer (underneath said dummy transistor gate) are removed and replaced by a metal gate.

Abstract translation: 形成硅 - 锗材料的翅片并用外延生长的硅材料层覆盖。 然后形成虚拟晶体管栅极以在鳍的沟道上延伸。 侧壁间隔物形成在虚拟晶体管栅极的两侧，并直接在外延硅层的顶部。 外延生长的源极和漏极区域形成在邻近侧壁间隔物的虚拟晶体管栅极的每一侧上。 虚拟晶体管栅极和外延硅层的一部分（在所述虚设晶体管栅极之下）被去除并由金属栅极代替。

公开(公告)号：US09391200B2

公开(公告)日：2016-07-12

申请号：US14308045

申请日：2014-06-18

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie ,  Chun-chen Yeh

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L21/311

CPC classification number: H01L29/7848 ,  H01L21/30625 ,  H01L21/3083 ,  H01L21/311 ,  H01L21/31144 ,  H01L29/66818 ,  H01L29/785

Abstract: Techniques and structures for controlling etch-back of a finFET fin are described. One or more layers may be deposited over the fin and etched. Etch-back of a planarization layer may be used to determine a self-limited etch height of one or more layers adjacent the fin and a self-limited etch height of the fin. Strain-inducing material may be formed at regions of the etched fin to induce strain in the channel of a finFET.

Abstract translation: 描述了用于控制finFET鳍片的回蚀的技术和结构。 一个或多个层可以沉积在翅片上并被蚀刻。 可以使用平坦化层的蚀刻来确定邻近鳍片的一个或多个层的自限制蚀刻高度以及翅片的自限制蚀刻高度。 应变诱发材料可以形成在蚀刻翅片的区域，以引起finFET通道中的应变。

公开(公告)号：US20160181395A1

公开(公告)日：2016-06-23

申请号：US14577316

申请日：2014-12-19

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Qing Liu ,  Bruce Doris ,  Gauri Karve

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/423 ,  H01L21/306 ,  H01L29/78 ,  H01L29/417

CPC classification number: H01L27/1211 ,  H01L21/02057 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/8258 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A fin of silicon-germanium material is formed and covered with an epitaxially grown layer of silicon material. A dummy transistor gate is then formed to extend over a channel of the fin. Sidewall spacers are formed on each side of the dummy transistor gate and directly on top of the expitaxial silicon layer. Epitaxially grown raised source and drain regions are formed on each side of the dummy transistor gate adjacent the sidewall spacers. The dummy transistor gate and a portion of the epitaxial silicon layer (underneath said dummy transistor gate) are removed and replaced by a metal gate.

公开(公告)号：US09306001B1

公开(公告)日：2016-04-05

申请号：US14685745

申请日：2015-04-14

Applicant: International Business Machines Corporation ,  Globalfoundries, Inc. ,  STMicroelectronics, Inc.

Inventor： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L21/761 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L27/12 ,  H01L21/8234 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/84

CPC classification number: H01L29/0638 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Embodiments are directed to a method of forming a leakage current stopper of a fin-type field effect transistor (FinFET). The method includes forming at least one fin having an active region, a non-active region and a channel region in the active region. The method further includes exposing a surface of the non-active region, wherein the exposed surface leads to a portion of the non-active region that is substantially underneath the channel region. The method further includes implanting dopants through the exposed surface of the non-active region to form the leakage current stopper region.

Abstract translation: 实施例涉及一种形成鳍式场效应晶体管（FinFET）的漏电流阻挡器的方法。 该方法包括在有源区中形成至少一个具有有源区，非有源区和沟道区的鳍。 该方法还包括暴露非有源区的表面，其中暴露的表面导致基本上在沟道区下面的非有源区的一部分。 该方法还包括通过非有源区的暴露表面注入掺杂剂以形成泄漏电流停止区。

公开(公告)号：US20150372140A1

公开(公告)日：2015-12-24

申请号：US14308045

申请日：2014-06-18

Applicant: STMicroelectronics, Inc ,  International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie ,  Chun-chen Yeh

IPC: H01L29/78 ,  H01L21/306 ,  H01L21/311 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/30625 ,  H01L21/3083 ,  H01L21/311 ,  H01L21/31144 ,  H01L29/66818 ,  H01L29/785

Abstract: Techniques and structures for controlling etch-back of a finFET fin are described. One or more layers may be deposited over the fin and etched. Etch-back of a planarization layer may be used to determine a self-limited etch height of one or more layers adjacent the fin and a self-limited etch height of the fin. Strain-inducing material may be formed at regions of the etched fin to induce strain in the channel of a finFET.

Abstract translation: 描述了用于控制finFET鳍片的回蚀的技术和结构。 一个或多个层可以沉积在翅片上并被蚀刻。 可以使用平坦化层的蚀刻来确定邻近鳍片的一个或多个层的自限制蚀刻高度以及翅片的自限制蚀刻高度。 应变诱发材料可以形成在蚀刻翅片的区域，以引起finFET通道中的应变。