公开(公告)号：US09437808B2

公开(公告)日：2016-09-06

申请号：US14887168

申请日：2015-10-19

Applicant: Intel Corporation

Inventor： Brian S. Doyle ,  Charles C. Kuo ,  David L. Kencke ,  Roksana Golizadeh Mojarad ,  Uday Shah

IPC: G11C11/00 ,  H01L43/02 ,  H01L43/12 ,  H01L43/08 ,  H01L27/22 ,  G11C11/155 ,  G11C11/16 ,  H01L43/10

CPC classification number: H01L43/02 ,  G11C11/155 ,  G11C11/161 ,  G11C11/1675 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: Spin transfer torque memory (STTM) devices incorporating a field plate for application of an electric field to reduce a critical current required for transfer torque induced magnetization switching. Embodiments utilize not only current-induced magnetic filed or spin transfer torque, but also electric field induced manipulation of magnetic dipole orientation to set states in a magnetic device element (e.g., to write to a memory element). An electric field generated by a voltage differential between an MTJ electrode and the field plate applies an electric field to a free magnetic layer of a magnetic tunneling junction (MTJ) to modulate one or more magnetic properties over at least a portion of the free magnetic layer.

公开(公告)号：US20160133829A1

公开(公告)日：2016-05-12

申请号：US14982128

申请日：2015-12-29

Applicant: Intel Corporation

Inventor： Charles C. Kuo ,  Kaan Oguz ,  Brian S. Doyle ,  Elijah V. Karpov ,  Roksana Golizadeh Mojarad ,  David L. Kencke ,  Robert S. Chau

IPC: H01L43/10

CPC classification number: H01L43/10 ,  G11C11/161 ,  H01F10/3286 ,  H01F10/329 ,  H01L43/065 ,  H01L43/08 ,  H01L43/12 ,  H01L43/14

Abstract: An embodiment includes a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier between the free and fixed layers; the tunnel barrier directly contacting a first side of the free layer; and an oxide layer directly contacting a second side of the free layer; wherein the tunnel barrier includes an oxide and has a first resistance-area (RA) product and the oxide layer has a second RA product that is lower than the first RA product. The MTJ may be included in a perpendicular spin torque transfer memory. The tunnel barrier and oxide layer form a memory having high stability with an RA product not substantively higher than a less table memory having a MTJ with only a single oxide layer. Other embodiments are described herein.

Abstract translation: 实施例包括在自由层和固定层之间包括自由磁性层，固定磁性层和隧道势垒的磁性隧道结（MTJ）; 所述隧道势垒直接接触所述自由层的第一侧; 和直接接触自由层的第二面的氧化物层; 其中所述隧道势垒包括氧化物并且具有第一电阻区域（RA）产物，并且所述氧化物层具有低于所述第一RA产物的第二RA产物。 MTJ可以包括在垂直旋转扭矩传递存储器中。 隧道势垒和氧化物层形成具有高稳定性的存储器，RA产物实质上高于具有仅具有单一氧化物层的MTJ的较少表存储器。 本文描述了其它实施例。

公开(公告)号：US11812600B2

公开(公告)日：2023-11-07

申请号：US16452099

申请日：2019-06-25

Applicant: Intel Corporation

Inventor： Seung Hoon Sung ,  Charles C. Kuo ,  Abhishek A. Sharma ,  Van H. Le ,  Jack Kavalieros

IPC: H10B12/00 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786

CPC classification number: H10B12/05 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78642 ,  H01L29/78696 ,  H10B12/036 ,  H10B12/33 ,  H10B12/482

Abstract: An integrated circuit includes one or more layers of insulating material defining a vertical bore with a first portion and a second portion. A capacitor structure is in the first portion of the vertical bore and includes a first electrode, a second electrode, and a dielectric between the first electrode and the second electrode. A transistor structure is in the second portion of the vertical bore and includes a third electrode extending into the second portion of the vertical bore, a layer of semiconductor material in contact with the first electrode and in contact with the second electrode, and a dielectric between the semiconductor material and the insulating material. A fourth electrode wraps around the transistor structure such that the dielectric is between the semiconductor material and the fourth electrode. The capacitor structure can be above or below the transistor structure in a self-aligned vertical arrangement.

公开(公告)号：US11295884B2

公开(公告)日：2022-04-05

申请号：US16329309

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Kaan Oguz ,  Kevin P. O'Brien ,  Brian S. Doyle ,  Charles C. Kuo ,  Mark L. Doczy

IPC: H01F10/32 ,  H01L43/02 ,  G11C11/16 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: A perpendicular spin transfer torque memory (pSTTM) device incorporates a magnetic tunnel junction (MTJ) device having a free magnetic stack that includes a plurality of magnetic layers interleaved with a plurality of non-magnetic insert layers. The layers are arranged such that the topmost and bottommost layers are magnetic layers. The stacked design decreases the damping of the MTJ free magnetic stack, beneficially reducing the write current required to write to the pSTTM device. The stacked design further increases the interface anisotropy, thereby beneficially improving the stability of the pSTTM device. The non-magnetic interface layer may include tantalum, molybdenum, tungsten, hafnium, or iridium, or a binary alloy containing at least two of tantalum, molybdenum, tungsten hafnium, or iridium.

公开(公告)号：US11031545B2

公开(公告)日：2021-06-08

申请号：US16327603

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Kaan Oguz ,  Kevin P. O'Brien ,  Brian S. Doyle ,  Mark L. Doczy ,  Charles C. Kuo ,  Daniel G. Ouellette ,  Christopher J. Wiegand ,  Md Tofizur Rahman ,  Brian Maertz

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: Systems, apparatus, and methods for magnetoresitive memory are described. An apparatus for magnetoresitive memory includes a fixed layer, a free layer, and a tunneling barrier between the fixed layer and the free layer. The free layer is a new alloy consisting of a composition of Cobalt (Co), Iron (Fe), and Boron (B) intermixed with a non-magnetic metal according to a ratio. A thin insert layer of CoFeB may optionally be added between the alloy and the tunneling barrier.

公开(公告)号：US10580973B2

公开(公告)日：2020-03-03

申请号：US16214306

申请日：2018-12-10

Applicant: INTEL CORPORATION

Inventor： Brian S. Doyle ,  Kaan Oguz ,  Charles C. Kuo ,  Mark L. Doczy ,  Satyarth Suri ,  David L. Kencke ,  Robert S. Chau ,  Roksana Golizadeh Mojarad

IPC: H01L43/02 ,  H01L43/08 ,  H01L27/22 ,  H01L43/12 ,  G11C11/16

Abstract: Techniques are disclosed for forming integrated circuit structures including a magnetic tunnel junction (MTJ), such as spin-transfer torque memory (STTM) devices, having magnetic contacts. The techniques include incorporating an additional magnetic layer (e.g., a layer that is similar or identical to that of the magnetic contact layer) such that the additional magnetic layer is coupled antiferromagnetically (or in a substantially antiparallel manner). The additional magnetic layer can help balance the magnetic field of the magnetic contact layer to limit parasitic fringing fields that would otherwise be caused by the magnetic contact layer. The additional magnetic layer may be antiferromagnetically coupled to the magnetic contact layer by, for example, including a nonmagnetic spacer layer between the two magnetic layers, thereby creating a synthetic antiferromagnet (SAF). The techniques can benefit, for example, magnetic contacts having magnetic directions that are substantially in-line or substantially in-plane with the layers of the MTJ stack.

公开(公告)号：US10439134B2

公开(公告)日：2019-10-08

申请号：US15117594

申请日：2014-03-25

Applicant: INTEL CORPORATION

Inventor： Prashant Majhi ,  Elijah V. Karpov ,  Uday Shah ,  Niloy Mukherjee ,  Charles C. Kuo ,  Ravi Pillarisetty ,  Brian S. Doyle ,  Robert S. Chau

IPC: H01L45/00 ,  H01L27/24

Abstract: Techniques are disclosed for forming non-planar resistive memory cells, such as non-planar resistive random-access memory (ReRAM or RRAM) cells. The techniques can be used to reduce forming voltage requirements and/or resistances involved (such as the resistance during the low-resistance state) relative to planar resistive memory cells for a given memory cell space. The non-planar resistive memory cell includes a first electrode, a second electrode, and a switching layer disposed between the first and second electrodes. The second electrode may be substantially between opposing portions of the switching layer, and the first electrode may be substantially adjacent to at least two sides of the switching layer, after the non-planar resistive memory cell is formed. In some cases, an oxygen exchange layer (OEL) may be disposed between the switching layer and one of the first and second electrodes to, for example, increase flexibility in incorporating materials in the cell.

公开(公告)号：US10403811B2

公开(公告)日：2019-09-03

申请号：US15503680

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Kevin P. O'Brien ,  Kaan Oguz ,  Brian S. Doyle ,  Mark L. Doczy ,  Charles C. Kuo ,  Robert S. Chau

IPC: G11C11/16 ,  H01L43/10 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01F10/32

Abstract: A material layer stack for a magnetic tunneling junction, the material layer stack including a fixed magnetic layer; a dielectric layer; a free magnetic layer; and an amorphous electrically-conductive seed layer, wherein the fixed magnetic layer is disposed between the dielectric layer and the seed layer. A non-volatile memory device including a material stack including an amorphous electrically-conductive seed layer; and a fixed magnetic layer juxtaposed and in contact with the seed layer. A method including forming an amorphous seed layer on a first electrode of a memory device; forming a material layer stack on the amorphous seed layer, the material stack including a dielectric layer disposed between a fixed magnetic layer and a free magnetic layer, wherein the fixed magnetic layer.

公开(公告)号：US10396211B2

公开(公告)日：2019-08-27

申请号：US15747925

申请日：2015-07-31

Applicant: Intel Corporation

Inventor： Elijah V. Karpov ,  Prashant Majhi ,  Roza Kotlyar ,  Niloy Mukherjee ,  Charles C. Kuo ,  Uday Shah ,  Ravi Pillarisetty ,  Robert S. Chau

IPC: H01L29/786 ,  H01L27/07 ,  H01L29/02 ,  H01L29/49 ,  H01L27/12 ,  H01L45/00 ,  H01L27/24

Abstract: A microelectronic device having a functional metal oxide channel may be fabricated on a microelectronic substrate that can be utilized in very large scale integration, such as a silicon substrate, by forming a buffer transition layer between the microelectronic substrate and the functional metal oxide channel. In one embodiment, the microelectronic device may be a microelectronic transistor with a source structure and a drain structure formed on the buffer transition layer, wherein the source structure and the drain structure abut opposing sides of the functional metal oxide channel and a gate dielectric is disposed between a gate electrode and the functional metal oxide channel. In another embodiment, the microelectronic device may be a two-terminal microelectronic device.

公开(公告)号：US10365894B2

公开(公告)日：2019-07-30

申请号：US15575334

申请日：2015-06-17

Applicant: Intel Corporation

Inventor： Charles C. Kuo ,  Justin S. Brockman ,  Juan G. Alzate Vinasco ,  Kaan Oguz ,  Kevin P. O'Brien ,  Brian S. Doyle ,  Mark L. Doczy ,  Satyarth Suri ,  Robert S. Chau ,  Prashant Majhi ,  Ravi Pillarisetty ,  Elijah V. Karpov

IPC: G06F7/58 ,  H01L43/02 ,  H01L43/08

Abstract: Described is an apparatus which comprises: a magnetic tunneling junction (MTJ) device with out-of-plane magnetizations for its free and fixed magnetic layers, and configured to have a magnetization offset away from a center and closer to a switching threshold of the MTJ device; and logic for generating random numbers according to a resistive state of the MTJ device.