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    Semiconductor memory device having row-related circuit operating at high speed
    41.
    发明授权
    Semiconductor memory device having row-related circuit operating at high speed 失效
    具有行相关电路的半导体存储器件以高速工作

    公开(公告)号：US06507532B1

    公开(公告)日：2003-01-14

    申请号：US09722687

    申请日：2000-11-28

    申请人： Takeshi Fujino ,  Kazunari Inoue ,  Akira Yamazaki ,  Kazutami Arimoto

    发明人： Takeshi Fujino ,  Kazunari Inoue ,  Akira Yamazaki ,  Kazutami Arimoto

    IPC分类号： G11C800

    CPC分类号： G11C8/12 ,  G11C8/18 ,  G11C11/4087

    摘要： A central row-related control circuit transmits an internal row address signal to each memory sub block in banks of memory mats asynchronously with an external clock signal, and latches a block selection signal for specifying a memory sub block synchronously with an internal clock signal for one clock cycle period for transmission to each memory sub block. A spare determination circuit performs spare determination asynchronously with the clock signal. A semiconductor memory device easily adaptable to bank expansion without increase of the chip area and capable of implementing a high speed access can be provided.

    摘要翻译： 中央行相关控制电路与外部时钟信号异步地将内部行地址信号发送到存储器存储体中的每个存储器子块，并且与一个内部时钟信号同步地锁存用于指定存储器子块的块选择信号 时钟周期，用于传输到每个存储器子块。 备用确定电路与时钟信号异步地执行备用确定。 可以提供容易适应银行扩张的半导体存储器件，而不增加芯片面积并且能够实现高速存取。

    Dynamic semiconductor memory device
    43.
    发明授权
    Dynamic semiconductor memory device 失效
    动态半导体存储器件

    公开(公告)号：US6151244A

    公开(公告)日：2000-11-21

    申请号：US176029

    申请日：1998-10-21

    申请人： Takeshi Fujino ,  Kazutami Arimoto

    发明人： Takeshi Fujino ,  Kazutami Arimoto

    IPC分类号： H01L21/8247 ,  G11C11/401 ,  G11C11/4074 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/24

    CPC分类号： G11C11/401 ,  G11C11/4074

    摘要： Memory cell minimum units (MCU) formed of multi-bit one transistor/one capacitor type memory cells are repeatedly arranged in a column direction, and bit line contacts (BCT) are shifted in the column direction relative to a row direction. The bit line contacts are repeatedly shifted with a prescribed number of bit lines as a unit. A set of a read bit line onto which memory cell data are read and a reference bit line supplying a reference potential can be obtained by controlling the voltage of cell plate lines and bit lines for each set of bit lines. Accordingly, a memory cell occupation area can be reduced and sensing operation in the folded bit line arrangement is possible. Consequently, a memory cell occupation area per one bit can be dramatically reduced and sensing operation in the folded bit line arrangement can be performed.

    摘要翻译： 由多位一晶体管/一电容型存储单元形成的存储单元最小单元（MCU）沿列方向重复排列，并且位线接触（BCT）相对于行方向在列方向上偏移。 位线接点以规定数量的位线为单位重复移位。 通过控制每组位线的单元板线和位线的电压，可以获得读取存储单元数据的读取位线和提供参考电位的参考位线的集合。 因此，可以减小存储器单元占用面积，并且折叠位线布置中的感测操作是可能的。 因此，可以显着减少每一位的存储单元占用面积，并且可以执行折叠位线布置中的感测操作。

    Semiconductor memory device having hierarchical word line structure
    44.
    发明授权
    Semiconductor memory device having hierarchical word line structure 失效
    具有分层字线结构的半导体存储器件

    公开(公告)号：US5966340A

    公开(公告)日：1999-10-12

    申请号：US960286

    申请日：1997-10-29

    申请人： Takeshi Fujino ,  Masaki Tsukude

    发明人： Takeshi Fujino ,  Masaki Tsukude

    IPC分类号： G11C11/407 ,  G11C7/18 ,  G11C8/14 ,  G11C11/401 ,  G11C11/409 ,  G11C8/00

    CPC分类号： G11C7/18 ,  G11C8/14

    摘要： Conductive lines for electrostatic shielding including at least one signal line are arranged between a global data I/O bus line and a ground line transmitting a ground voltage to a nonselected word line through a sub-decoder. Capacitive coupling between bus lines included in the global data I/O bus and the ground line is suppressed, and floating up of a ground voltage on the nonselected word line is prevented.

    摘要翻译： 包括至少一条信号线的用于静电屏蔽的导电线被布置在全局数据I / O总线与通过子解码器将接地电压发送到非选择字线的接地线之间。 包含在全局数据I / O总线和地线之间的总线之间的电容耦合被抑制，并且防止非选定字线上的接地电压浮起。

    Method of manufacturing semiconductor memory device capable of readily repairing defective portion resulting from mask defect
    45.
    发明授权
    Method of manufacturing semiconductor memory device capable of readily repairing defective portion resulting from mask defect 失效
    制造能够容易地修复由掩模缺陷产生的缺陷部分的半导体存储器件的制造方法

    公开(公告)号：US5960253A

    公开(公告)日：1999-09-28

    申请号：US899814

    申请日：1997-07-24

    申请人： Takeshi Fujino

    发明人： Takeshi Fujino

    IPC分类号： H01L21/3205 ,  H01L21/82 ,  H01L21/8242 ,  H01L23/52 ,  H01L27/108 ,  H01L21/00

    CPC分类号： H01L27/10897

    摘要： A method of manufacturing a semiconductor memory device includes a first step of forming a plurality of memory cells with a redundancy portion through fine patterning, a second step of searching a defect in masks used in the fine patterning and a third step of forming offset via holes so as to interconnect the redundancy portion instead of a defective portion identified by an inspection in non-fine patterning conducted after the fine patterning.

    摘要翻译： 一种制造半导体存储器件的方法包括：通过精细图案化形成具有冗余部分的多个存储单元的第一步骤，在精细图案化中使用的掩模中搜索缺陷的第二步骤和形成偏移通孔的第三步骤 以便在精细图案化之后进行的非精细图案中互连冗余部分而不是通过检查识别的缺陷部分。

    TAMPER-RESISTANT MEMORY INTEGRATED CIRCUIT AND ENCRYPTION CIRCUIT USING SAME
    46.
    发明申请
    TAMPER-RESISTANT MEMORY INTEGRATED CIRCUIT AND ENCRYPTION CIRCUIT USING SAME 有权
    使用相同的阻抗记忆体集成电路和加密电路

    公开(公告)号：US20130129083A1

    公开(公告)日：2013-05-23

    申请号：US13812628

    申请日：2010-07-28

    申请人： Takeshi Fujino

    发明人： Takeshi Fujino

    IPC分类号： G11C8/08 ,  H04L9/00 ,  G11C7/12 ,  H04L9/28 ,  G11C8/00 ,  G11C7/00 ,  G06F7/58

    CPC分类号： G11C8/08 ,  G06F7/584 ,  G11C7/24 ,  H04L9/003 ,  H04L9/0618 ,  H04L2209/127

    摘要： The present invention provides an integrated memory circuit applicable to an S-box of a cryptographic circuit, the integrated memory circuit having a row decoder, a column decoder, and a sense amplifier composed of a domino-RSL circuit, wherein data reading and data writing from/to memory cells of a memory cell array are performed via two complementary bit lines, and the transition probability of a signal line is equalized by input of random-number data supplied from a random-number generating circuit using an arbiter circuit.

    摘要翻译： 本发明提供了一种适用于密码电路的S盒的集成存储器电路，该集成存储电路具有行解码器，列解码器和由多米诺骨牌RSL电路组成的读出放大器，其中数据读取和数据写入 通过两条互补位线执行存储单元阵列的存储单元的存储单元，通过使用仲裁器电路从随机数产生电路输入的随机数数据的输入来均衡信号线的转移概率。

    Fuel cell power supply device
    47.
    发明授权
    Fuel cell power supply device 失效
    燃料电池供电装置

    公开(公告)号：US07994751B2

    公开(公告)日：2011-08-09

    申请号：US12222292

    申请日：2008-08-06

    申请人： Minoru Noguchi ,  Mitsuaki Hirakawa ,  Takeshi Fujino ,  Eisuke Komazawa

    发明人： Minoru Noguchi ,  Mitsuaki Hirakawa ,  Takeshi Fujino ,  Eisuke Komazawa

    IPC分类号： H01M10/44 ,  G05F1/10 ,  B60K1/00 ,  G08B3/00

    CPC分类号： H01M8/04619 ,  B60L1/006 ,  B60L11/005 ,  B60L11/1868 ,  B60L11/1885 ,  B60L11/1887 ,  H01M8/04626 ,  H01M8/0494 ,  H01M8/04947 ,  H01M10/488 ,  H01M16/003 ,  H01M16/006 ,  H01M2250/20 ,  H02J7/345 ,  H02J2001/004 ,  Y02T10/7022 ,  Y02T10/7066 ,  Y02T90/32 ,  Y02T90/34

    摘要： A fuel cell power supply device capable of externally supplying electric power in a stable manner is provided. The fuel cell power supply device includes a fuel cell (1), a capacitor (2) connected in parallel to the fuel cell, a voltage boosting means (3) having an input unit connected in parallel to the fuel cell and the capacitor and an output unit connected to a load (M), and for boosting the output voltages of the fuel cell and the capacitor to supply electric power by the boosted voltages to the load, a secondary battery (6) connected to the output unit of the voltage boosting means via a voltage conversion means (7), a first electric power supply unit (10) connected in parallel to the fuel cell and the capacitor and capable of externally supplying electric power, and an electric power supply control means (30) for controlling supply of electric power from the fuel cell, the capacitor, and the secondary battery to the first electric power supply unit, based on the output of the fuel cell and the charge levels of the capacitor and the secondary battery, in a range where the charge level of the capacitor is not lower than its discharge threshold value and the charge level of the secondary battery is not lower than its discharge threshold value.

    摘要翻译： 提供能够以稳定的方式从外部供给电力的燃料电池电源装置。 燃料电池电源装置包括燃料电池（1），与燃料电池并联连接的电容器（2），具有与燃料电池和电容器并联连接的输入单元的升压装置（3）和 连接到负载（M）的输出单元，并且用于升压燃料电池和电容器的输出电压以通过升压电压向负载提供电力;二次电池（6），其连接到升压的输出单元 通过电压转换装置（7），与燃料电池并联连接并能够从外部供电的第一电力供应单元（10）和用于控制供电的电力供应控制装置（30） 基于燃料电池的输出和电容器和二次电池的充电电平，从燃料电池，电容器和二次电池到第一电力供应单元的电力的电力在充电水平 的 电容器不低于其放电阈值，并且二次电池的充电水平不低于其放电阈值。

    Power supply device for vehicles
    48.
    发明授权
    Power supply device for vehicles 失效
    车辆供电装置

    公开(公告)号：US07994745B2

    公开(公告)日：2011-08-09

    申请号：US12222034

    申请日：2008-07-31

    申请人： Takeshi Fujino ,  Mitsuaki Hirakawa ,  Minoru Noguchi ,  Eisuke Komazawa

    发明人： Takeshi Fujino ,  Mitsuaki Hirakawa ,  Minoru Noguchi ,  Eisuke Komazawa

    IPC分类号： H02P3/14

    CPC分类号： B60L11/1887 ,  B60L3/0046 ,  B60L3/04 ,  B60L7/14 ,  B60L11/1803 ,  B60L11/1861 ,  B60L11/1872 ,  B60L15/2009 ,  B60L2210/10 ,  B60L2240/423 ,  B60L2240/429 ,  B60L2240/545 ,  B60L2240/547 ,  Y02T10/645 ,  Y02T10/7011 ,  Y02T10/7044 ,  Y02T10/705 ,  Y02T10/7216 ,  Y02T10/7275 ,  Y02T90/34

    摘要： A power supply device for vehicles, output units (10a, 10b) thereof are connected to a motor (5), includes a fuel cell (1) which is connected to the output units (10a, 10b), a capacitor (2) which is connected in parallel to the fuel cell (1), a lithium ion battery (21) which is connected in parallel to the capacitor (2) through a DC/DC converter (20), and a current control means (32) which limits an output current of the lithium ion battery (21) to at most an output upper-limit current (Ibout_lmt) when power is supplied to the motor (5) from the lithium ion battery (21) during a power running operation of the motor (5), and limits an input current into the lithium ion battery (21) to at most an input upper-limit current smaller than the output upper-limit current (Ibin_lmt) through the DC/DC converter (20) when regenerative power of the motor (5) is recovered into the lithium ion battery (21) during a regenerative operation of the motor (5).

    摘要翻译： 一种用于车辆的供电装置，其输出单元（10a，10b）连接到电动机（5），包括连接到输出单元（10a，10b）的燃料电池（1），电容器（2） 与燃料电池（1）并联连接，通过DC / DC转换器（20）与电容器（2）并联连接的锂离子电池（21），以及电流控制装置（32），其限制 在电动机的动力运行期间从锂离子电池（21）向电动机（5）供电时，锂离子电池（21）的输出电流至多为输出上限电流（Ibout_lmt） 5），并且通过DC / DC转换器（20）将输入电流限制到锂离子电池（21）的至少一个输入上限电流小于通过DC / DC转换器（20）的输出上限电流（Ibin_lmt），当再生电力 在马达（5）的再生运转期间，马达（5）被回收到锂离子电池（21）中。

    IMAGE HEATING APPARATUS
    49.
    发明申请
    IMAGE HEATING APPARATUS 有权
    图像加热装置

    公开(公告)号：US20110052280A1

    公开(公告)日：2011-03-03

    申请号：US12853594

    申请日：2010-08-10

    申请人： Takeshi Fujino

    发明人： Takeshi Fujino

    IPC分类号： G03G15/20

    CPC分类号： G03G15/2042

    摘要： An image heating apparatus includes a rotatable image heating member including an electroconductive layer; a pressing member, press-contacting the image heating member, for forming a nip in which an image on a recording material is to be heated; an urging member, provided inside the image heating member, for urging the image heating member toward the pressing member; and an excitation coil for induction-heating the electroconductive layer. When a length of the image heating member with respect to a rotational axis direction of the image heating member is Lb, a length of the pressing member with respect to the rotational axis direction is Lr, an outside distance of bent portions of the excitation coil at both end portions of the excitation coil with respect to the rotational axis direction is LcoilA, and an inside distance of the bent portions with respect to the rotational axis direction is LcoilB, the lengths Lb and Lr and the distance LcoilA and LcoilB satisfy the following relationship: LcoilA>Lb>Lr>LcoilB.

    摘要翻译： 图像加热装置包括可旋转图像加热构件，其包括导电层; 加压构件，与图像加热构件压接，用于形成记录材料上的图像将被加热的辊隙; 设置在图像加热部件内部的用于将图像加热部件推向按压部件的施力部件; 以及用于感应加热导电层的激励线圈。 当图像加热构件相对于图像加热构件的旋转轴线方向的长度为Lb时，按压构件相对于旋转轴线方向的长度为Lr，励磁线圈的弯曲部分的外部距离在 励磁线圈的相对于旋转轴方向的两端部为LcoilA，弯曲部相对于旋转轴方向的内侧距离为LcoilB，长度Lb，Lr以及距离LcoilA，LcoilB满足以下关系 ：Lcoil> Lb> Lr> LcoilB。