公开(公告)号：US07339190B2

公开(公告)日：2008-03-04

申请号：US11308710

申请日：2006-04-25

Applicant: Hung-Tse Chen ,  Chi-Lin Chen ,  Yu-Cheng Chen

Inventor： Hung-Tse Chen ,  Chi-Lin Chen ,  Yu-Cheng Chen

IPC: H01L29/76

CPC classification number: H01L29/78696 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/12 ,  H01L27/1285 ,  H01L29/04 ,  H01L29/4234 ,  H01L29/66757 ,  H01L29/66833 ,  H01L29/78675 ,  H01L29/792

Abstract: A memory cell suitable for being disposed over a substrate is provided. The memory cell includes a poly-silicon island, a first dielectric layer, a trapping layer, a second dielectric layer and a control gate. The poly-silicon island is disposed on the substrate and includes a source region, a drain region and a channel region located between the source and drain regions. The channel region has a plurality of regularly arranged tips thereon. The first dielectric layer is disposed on the poly-silicon island. The trapping layer is disposed on the first dielectric layer. The second dielectric layer is disposed on the trapping layer. The control gate is disposed on the second dielectric layer. The memory cell mentioned above can be integrated into the LTPS-LCD panel or OLED panel.

Abstract translation: 提供了适于布置在基板上的存储单元。 存储单元包括多晶硅岛，第一介电层，俘获层，第二介质层和控制栅极。 多硅岛设置在衬底上，并且包括源极区，漏极区和位于源极和漏极区之间的沟道区。 通道区域在其上具有多个规则排列的尖端。 第一介电层设置在多晶硅岛上。 捕获层设置在第一介电层上。 第二介质层设置在捕获层上。 控制栅极设置在第二电介质层上。 上述存储单元可以集成到LTPS-LCD面板或OLED面板中。

公开(公告)号：US20070105373A1

公开(公告)日：2007-05-10

申请号：US11270862

申请日：2005-11-09

Applicant: Liang-Tang Wang ,  Chi-Lin Chen ,  I-Hsuan Peng ,  Jung-Fang Chang ,  Chin-Jen Huang

Inventor： Liang-Tang Wang ,  Chi-Lin Chen ,  I-Hsuan Peng ,  Jung-Fang Chang ,  Chin-Jen Huang

IPC: H01L21/44

CPC classification number: H01L21/02532 ,  C23C16/0272 ,  C23C16/24 ,  C23C16/5096 ,  H01L21/02422 ,  H01L21/0262 ,  H01L27/1214

Abstract: A method for forming a polysilicon film in a plasma-assisted chemical vapor deposition (CVD) system including a chamber in which a first electrode and a second electrode spaced apart from the first electrode are provided comprises providing a substrate on the second electrode, the substrate including a surface exposed to the first electrode, applying a first power to the first electrode for generating a plasma in the chamber, applying a second power to the second electrode during a nucleation stage of the polysilicon film for ion bombarding the surface of the substrate, and flowing an erosive gas into the chamber.

Abstract translation: 一种在等离子体辅助化学气相沉积（CVD）系统中形成多晶硅膜的方法，包括：设置有与第一电极间隔开的第一电极和第二电极的腔室，包括在第二电极上设置衬底， 包括暴露于第一电极的表面，向第一电极施加第一功率以在腔室中产生等离子体，在用于离子轰击衬底表面的多晶硅膜的成核阶段期间向第二电极施加第二功率， 并将侵蚀性气体流入室内。

公开(公告)号：US20070085115A1

公开(公告)日：2007-04-19

申请号：US11308612

申请日：2006-04-12

Applicant: Hung-Tse Chen ,  Chi-Lin Chen ,  Yu-Cheng Chen ,  Chi-Wen Chen ,  Ting-Chang Chang

Inventor： Hung-Tse Chen ,  Chi-Lin Chen ,  Yu-Cheng Chen ,  Chi-Wen Chen ,  Ting-Chang Chang

IPC: H01L31/113 ,  H01L31/062 ,  H01L21/84 ,  H01L21/00

CPC classification number: H01L27/1214 ,  H01L29/40117 ,  H01L29/66833

Abstract: A memory cell, suitable for being disposed on a substrate, comprises a poly-Si island, a first dielectric layer, a trapping layer, a second dielectric layer and a control gate. The poly-Si island is disposed on the substrate and includes a source doped region, a drain doped region and a channel region there-between. The first dielectric layer is disposed on the poly-Si island, the trapping layer is disposed on the first dielectric layer, the second dielectric layer is disposed on the trapping layer and the control gate is disposed on the second dielectric layer. The above-described memory cell can be integrated into the manufacturing process of a low temperature polysilicon LCD panel (LTPS LCD panel) or an organic light emitting display panel (OLED panel).

Abstract translation: 适用于设置在基板上的存储单元包括多晶硅岛，第一介电层，俘获层，第二介电层和控制栅。 多晶硅岛设置在衬底上，包括源极掺杂区，漏极掺杂区和其间的沟道区。 第一介电层设置在多晶硅岛上，俘获层设置在第一介电层上，第二介电层设置在俘获层上，控制栅设置在第二介质层上。 上述存储单元可以集成到低温多晶硅LCD面板（LTPS LCD面板）或有机发光显示面板（OLED面板）的制造过程中。

公开(公告)号：US07161226B2

公开(公告)日：2007-01-09

申请号：US11131084

申请日：2005-05-17

Applicant: Yu-Cheng Chen ,  Chi-Lin Chen

Inventor： Yu-Cheng Chen ,  Chi-Lin Chen

IPC: H01L29/00

CPC classification number: H01L23/5221 ,  G02F1/136286 ,  G02F2001/13629 ,  H01L27/12 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A multi-layered wire structure includes a substrate, a plurality of first conductive lines formed in a first layer over the substrate extending in parallel to each other in a first direction, a plurality of second conductive lines formed in a second layer over the first layer extending in parallel to each other in a second direction orthogonal to the first direction, a plurality of sets of third conductive lines formed in the second layer extending in the first direction, each set of third conductive lines corresponding to one of the first conductive lines, and a plurality of sets of conductive paths formed between the first layer and the second layer, each set of conductive paths corresponding to one of the first conductive lines and one set of third conductive lines and electrically connecting the corresponding first conductive line to the corresponding set of third conductive lines.

Abstract translation: 一种多层导线结构，包括：基板，形成在第一层上的多个第一导电线，该第一导电线在基板上沿着第一方向彼此平行地延伸;多个第二导电线，形成在第一层上的第一层 在与第一方向正交的第二方向上彼此平行地延伸的多个第三导线组，所述第二导电线形成在第一方向上延伸，每组第三导线对应于第一导线之一， 以及形成在所述第一层和所述第二层之间的多组导电路径，每组导电路径对应于所述第一导电线中的一条和一组第三导电线，并将相应的第一导电线电连接到相应的集合 的第三导线。

公开(公告)号：US07060541B2

公开(公告)日：2006-06-13

申请号：US10673325

申请日：2003-09-30

Applicant: Chi-Shen Lee ,  Cheng-Chung Chen ,  Chi-Lin Chen ,  Chai-Yuan Sheu

Inventor： Chi-Shen Lee ,  Cheng-Chung Chen ,  Chi-Lin Chen ,  Chai-Yuan Sheu

IPC: H01L21/00 ,  H01L21/84

CPC classification number: H01L27/124 ,  H01L27/1255

Abstract: A method of fabricating a thin film transistor (TFT) array involves ion replacement by oxidation-reduction processes for implementing the metal wiring layout of TFT-LCDs. This can overcome metal etching difficulties and achieve automatic alignment. The method of the invention replaces traditional lithographic etching techniciues.

Abstract translation: 制造薄膜晶体管（TFT）阵列的方法涉及通过用于实现TFT-LCD的金属布线布局的氧化还原处理的离子替换。 这可以克服金属蚀刻困难，实现自动对准。 本发明的方法取代了传统的光刻蚀刻技术。

公开(公告)号：US20050073619A1

公开(公告)日：2005-04-07

申请号：US10687759

申请日：2003-10-20

Applicant: Yu-Cheng Chen ,  Chi-Lin Chen

Inventor： Yu-Cheng Chen ,  Chi-Lin Chen

IPC: G09F9/30 ,  G02F1/1362 ,  H01L23/522 ,  H01L27/12 ,  G02F1/136

CPC classification number: H01L27/12 ,  G02F1/136286 ,  H01L23/5221 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A multi-layered complementary wire structure and a manufacturing method thereof are disclosed, comprising a first wire and a second wire. Each of the first and the second wires comprises a main line and a plurality of branch lines located in a different layer from the main line. A plurality contact holes are formed in an insulating layer between the first wire and the second wire to connect the main line of the first wire and the branch lines of the first wire, and connect the main line of the second wire and the branch lines of the second wire. The main line of the first wire is insulated and crossed with the main line of the second wire. The main line of the first wire and the branch lines of the second wire are insulated with each other and located in the same layer. The main line of the second wire and the branch lines of the first wire are insulated with each other and located in the same layer.

Abstract translation: 公开了一种多层互补线结构及其制造方法，包括第一线和第二线。 第一和第二导线中的每一个包括主线和位于与主线不同的层中的多个分支线。 在第一线和第二线之间的绝缘层中形成多个接触孔，以连接第一线的主线和第一线的分支线，并将第二线的主线和 第二根线。 第一根导线的主线绝缘并与第二根导线的主线交叉。 第一线的主线和第二线的分支线彼此绝缘并位于同一层中。 第二线的主线和第一线的分支线彼此绝缘并位于同一层中。

公开(公告)号：US20050048407A1

公开(公告)日：2005-03-03

申请号：US10673326

申请日：2003-09-30

Applicant: Chi-Shen Lee ,  Yung-Fu Wu ,  Chi-Lin Chen ,  Cheng-Chung Chen

Inventor： Chi-Shen Lee ,  Yung-Fu Wu ,  Chi-Lin Chen ,  Cheng-Chung Chen

IPC: G02F1/136 ,  G02F1/1362 ,  G02F1/1368 ,  G03F7/00 ,  H01L21/336 ,  H01L21/77 ,  H01L27/12 ,  H01L27/13 ,  H01L29/786

CPC classification number: G02F1/1368 ,  G02F1/136213 ,  H01L27/1255 ,  H01L27/1288

Abstract: A method of manufacturing a TFT array panel for a LCD disclosers that the gate electrode wiring, transparent conducting electrode, and the first electrode of the storage capacity are formed while the first mask is processing. Then, the selective deposition method is used to process the growth of the first metal wiring. This, therefore, can reduce the numbers of the mask processes. Further, the metal deposition with photo-resist lift-off step is used to implement the layout of the second metal wiring for the consequent transmission lines in the manufacturing process. Finally, the process of the passivation layer deposition is used to implement associated circuits of a TFT array panel for a LCD. The TFT array panel for a LCD for manufacturing circuits can simplify the manufacturing process and reduce the cost.

Abstract translation: 制造LCD阵列面板的方法公开了在第一掩模处理期间形成栅电极布线，透明导电电极和存储容量的第一电极。 然后，选择性沉积法用于处理第一金属布线的生长。 因此，这可以减少掩模处理的数量。 此外，利用光刻胶剥离工序进行金属蒸镀，以在制造工序中实现用于后续传输线的第二金属布线的布局。 最后，钝化层沉积的过程用于实现用于LCD的TFT阵列面板的相关电路。 用于制造电路的LCD的TFT阵列面板可以简化制造工艺并降低成本。

公开(公告)号：US08981209B2

公开(公告)日：2015-03-17

申请号：US13478345

申请日：2012-05-23

Applicant: I-Min Chan ,  Chi-Lin Chen

Inventor： I-Min Chan ,  Chi-Lin Chen

IPC: H01L31/05 ,  H01L31/02 ,  H01L31/0465

CPC classification number: H01L31/02013 ,  H01L31/0201 ,  H01L31/0465 ,  H01L31/05 ,  Y02E10/50

Abstract: A photovoltaic module includes a substrate, a plurality of cell sets, a first collecting electrode and a second collecting electrode. The cell sets are disposed on the substrate. Each of the cell sets includes a plurality of cell units, a bottom connecting electrode and an upper connecting electrode. The plurality of cell units are electrically connected to each other in series. The cell units are electrically connected between the bottom connecting electrode and the upper connecting electrode. The first collecting electrode is disposed on the substrate and is electrically connected to the bottom connecting electrode of every cell set. The second collecting electrode is disposed on the substrate and is electrically connected to the upper connecting electrode of every cell set. The second collecting electrode and the cell sets are substantially made of the same layer.

Abstract translation: 光伏模块包括基板，多个电池组，第一集电电极和第二集电极。 电池组设置在基板上。 每个单元组包括多个单元单元，底部连接电极和上部连接电极。 多个电池单元彼此串联电连接。 电池单元电连接在底部连接电极和上连接电极之间。 第一收集电极设置在基板上，并且电连接到每个电池组的底部连接电极。 第二集电电极设置在基板上并与每个电池组的上连接电极电连接。 第二收集电极和电池组基本上由相同的层制成。

公开(公告)号：US08259087B2

公开(公告)日：2012-09-04

申请号：US12755422

申请日：2010-04-07

Applicant: Ke-Horng Chen ,  Chi-Lin Chen ,  Yi-Chun Chen ,  Chih-Chung Chen ,  Chia-Lin Liu ,  Huai-An Li ,  Chi-Neng Mo

Inventor： Ke-Horng Chen ,  Chi-Lin Chen ,  Yi-Chun Chen ,  Chih-Chung Chen ,  Chia-Lin Liu ,  Huai-An Li ,  Chi-Neng Mo

IPC: G06F3/045

CPC classification number: G06F3/044

Abstract: In a capacitance sensing analog circuit of a touch panel sensing circuit, by raising a magnitude of a current flowing through a sensing capacitor to form an amplified sensing capacitance, while sensing the amplified sensing capacitance with the aid of pulse width modulation signals, higher resolution of the original sensing capacitance may thus be achieved. Besides, by using a self-calibrating capacitance sensing circuit on the touch panel sensing circuit, linear errors and DC errors of an output signal of the capacitance sensing analog circuit may be filtered off, and thereby resolution of a capacitance amplifying ratio may be effectively raised so as to relieve errors within the capacitance amplifying ratio caused by noises.

Abstract translation: 在触摸面板感测电路的电容感测模拟电路中，通过提高流经感测电容器的电流的大小以形成放大的感测电容，同时借助脉冲宽度调制信号感测放大的感测电容，更高的分辨率 因此可以实现原始感测电容。 此外，通过在触摸面板感测电路上使用自校准电容感测电路，可以滤除电容感测模拟电路的输出信号的线性误差和DC误差，从而可以有效地提高电容放大比的分辨率 以减轻由噪声引起的电容放大比例中的误差。

公开(公告)号：US20110254468A1

公开(公告)日：2011-10-20

申请号：US12831231

申请日：2010-07-06

Applicant: Ke-Horng Chen ,  Chi-Lin Chen ,  Yao-Yi Yang ,  Ling Li ,  Chia-Lin Liu ,  Chi-Neng Mo

Inventor： Ke-Horng Chen ,  Chi-Lin Chen ,  Yao-Yi Yang ,  Ling Li ,  Chia-Lin Liu ,  Chi-Neng Mo

IPC: H05B37/02

CPC classification number: H05B33/0818 ,  H05B33/0815

Abstract: A voltage converter for use in a backlight module stores energy of an input voltage using an inductor and outputs a plurality of output voltages accordingly. The charging path of the inductor is controlled according to the first output voltage so that the first output voltage can be stabilized. The discharging paths from the inductor to other output voltages are controlled according to the differences between other output voltages and the first output voltage so that other output voltages can also be stabilized.

Abstract translation: 用于背光模块的电压转换器使用电感器存储输入电压的能量并相应地输出多个输出电压。 根据第一输出电压来控制电感器的充电路径，使得第一输出电压可以稳定。 根据其他输出电压和第一输出电压之间的差异，从电感器到其他输出电压的放电路径进行控制，以便其他输出电压也可以稳定。