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    Method to form and/or isolate vertical transistors
    41.
    发明授权
    Method to form and/or isolate vertical transistors 有权
    形成和/或隔离垂直晶体管的方法

    公开(公告)号：US06511884B1

    公开(公告)日：2003-01-28

    申请号：US09972503

    申请日：2001-10-09

    申请人： Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan

    发明人： Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan

    IPC分类号： H01L21336

    CPC分类号： H01L29/66666 ,  H01L29/7827

    摘要： A method of fabricating an isolated vertical transistor comprising the following steps. A wafer having a first implanted region selected from the group comprising a source region and a drain region is provided. The wafer further includes STI areas on either side of a center transistor area. The wafer is patterned down to the first implanted region to form a vertical pillar within the center transistor area using a patterned hardmask. The vertical pillar having side walls. A pad dielectric layer is formed over the wafer, lining the vertical pillar. A nitride layer is formed over the pad dielectric layer. The structure is patterned and etched through the nitride layer and the pad dielectric layer; and into the wafer within the STI areas to form STI trenches within the wafer. The STI trenches are filled with insulative material to form STIs within STI trenches. The patterned nitride and pad dielectric layers are removed. The patterned hardmask is removed. Gate oxide is grown over the exposed portions of the wafer and the vertical pillar. Spacer gates are formed over the gate oxide lined side walls of the vertical pillar. Spacer gate implants are formed within the spacer gates, and a second implanted region is formed within the vertical pillar selected from the group consisting of a drain region and a source region that is not the same as the first implanted region to complete formation of the isolated vertical transistor.

    摘要翻译： 一种制造隔离垂直晶体管的方法，包括以下步骤。 提供具有从包括源极区域和漏极区域的组中选择的第一注入区域的晶片。 该晶片还包括在中心晶体管区域两侧的STI区域。 将晶片图案化到第一注入区域，以使用图案化的硬掩模在中心晶体管区域内形成垂直柱。 具有侧壁的立柱。 在晶片上形成衬垫介质层，衬在垂直柱上。 在焊盘介电层上形成氮化物层。 该结构被图案化并蚀刻通过氮化物层和焊盘介电层; 并进入STI区域内的晶片，以在晶片内形成STI沟槽。 STI沟槽填充有绝缘材料，以在STI沟槽内形成STI。 图案化的氮化物和焊盘介电层被去除。 去除图案化的硬掩模。 栅极氧化物生长在晶片和垂直柱的暴露部分上。 在垂直柱的栅极氧化物衬里侧壁上形成间隔栅极。 间隔栅极内部形成间隔栅极，并且在垂直柱内形成第二注入区，该垂直柱选自由漏极区域和不同于第一注入区域的源极区域组成的组，以完成孤立的 垂直晶体管。

    Method to form a recessed source drain on a trench side wall with a replacement gate technique
    43.
    发明授权
    Method to form a recessed source drain on a trench side wall with a replacement gate technique 有权
    用替代栅极技术在沟槽侧壁上形成凹陷源极漏极的方法

    公开(公告)号：US06380088B1

    公开(公告)日：2002-04-30

    申请号：US09764241

    申请日：2001-01-19

    申请人： Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng

    发明人： Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng

    IPC分类号： H01L21302

    CPC分类号： H01L29/66583 ,  H01L21/76224 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/4983 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66636

    摘要： An improved MOS transistor and method of making an improved MOS transistor. An MOS transistor having a recessed source drain on a trench sidewall with a replacement gate technique. Holes are formed in the shallow trench isolations, which exposes sidewall of the substrate in the active area. Sidewalls of the substrate are doped in the active area where holes are. Conductive material is then formed in the holes and the conductive material becomes the source and drain regions. The etch stop layer is then removed exposing sidewalls of the conductive material, and oxidizing exposed sidewalls of the conductive material is preformed. Spacers are formed on top of the pad oxide and on the sidewalls of the oxidized portions of the conductive material. The pad oxide layer is removed from the structure but not from under the spacers. A gate dielectric layer is formed on the substrate in the active area between the spacers; and a gate electrode is formed on said gate dielectric layer.

    摘要翻译： 一种改进的MOS晶体管和制造改进的MOS晶体管的方法。 MOS晶体管，具有沟槽侧壁上的凹陷源极漏极，具有替代栅极技术。 在浅沟槽隔离件中形成孔，其在有源区域中暴露衬底的侧壁。 在孔的有源区域中掺杂衬底的侧壁。 然后在孔中形成导电材料，并且导电材料变成源区和漏区。 然后去除蚀刻停止层，暴露导电材料的侧壁，并且对导电材料的暴露侧壁进行氧化预处理。 垫片形成在衬垫氧化物的顶部和导电材料的氧化部分的侧壁上。 衬垫氧化物层从结构中移除，但不从衬垫下方移除。 在间隔物之间​​的有源区域中的基板上形成栅极电介质层; 并且在所述栅极电介质层上形成栅电极。

    Method to form an elevated S/D CMOS device by contacting S/D through the contact of oxide
    45.
    发明授权
    Method to form an elevated S/D CMOS device by contacting S/D through the contact of oxide 失效
    通过使氧化物的接触使S / D接触来形成升高的S / D CMOS器件的方法

    公开(公告)号：US06306714B1

    公开(公告)日：2001-10-23

    申请号：US09713802

    申请日：2000-11-16

    申请人： Yang Pan ,  James Yongmeng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan

    发明人： Yang Pan ,  James Yongmeng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan

    IPC分类号： H01L21336

    CPC分类号： H01L21/76877 ,  H01L29/41783 ,  H01L29/66492 ,  H01L29/66583 ,  H01L29/6659 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of fabrication of an elevated source/drain (S/D) for a MOS device. A first insulating layer having a gate opening and source/drain openings is formed over a substrate. We form a LDD resist mask having opening over the source/drain openings over the first insulating layer. Ions are implanted through the source/drain openings. A first dielectric layer is formed on the substrate in the gate opening and source/drain openings. A gate is formed in the gate opening and raised source/drain (S/D) blocks in the source/drain openings. We remove the spacer blocks to form spacer block openings. We form second LDD regions by implanting ions through the spacer block openings. We form second spacer blocks in the spacer block openings. Plug opening are formed through the raised source/drain (S/D) blocks. Contact plugs are formed in the form plug opening.

    摘要翻译： 制造用于MOS器件的升高的源极/漏极（S / D）的方法。 在衬底上形成具有栅极开口和源极/漏极开口的第一绝缘层。 我们形成了在第一绝缘层上的源/漏开口上方具有开口的LDD抗蚀剂掩模。 离子通过源极/漏极开口植入。 在栅极开口和源极/漏极开口中的基板上形成第一电介质层。 栅极形成在源极/漏极开口中的栅极开路和升高的源极/漏极（S / D）块中。 我们移除间隔块以形成间隔块开口。 我们通过将离子注入间隔块开口形成第二LDD区域。 我们在间隔块开口中形成第二间隔块。 插头开口通过凸起的源极/漏极（S / D）块形成。 接触塞以形式的塞子开口形成。

    Method to form a smooth gate polysilicon sidewall in the fabrication of integrated circuits
    47.
    发明授权
    Method to form a smooth gate polysilicon sidewall in the fabrication of integrated circuits 有权
    在集成电路制造中形成平滑栅多晶硅侧壁的方法

    公开(公告)号：US06200887B1

    公开(公告)日：2001-03-13

    申请号：US09490133

    申请日：2000-01-24

    申请人： Palanivel Balasubramaniam ,  Narayanan Balasubramanian ,  Yelehanka Ramachandramurthy Pradeep ,  Arjun Kantimahanti

    发明人： Palanivel Balasubramaniam ,  Narayanan Balasubramanian ,  Yelehanka Ramachandramurthy Pradeep ,  Arjun Kantimahanti

    IPC分类号： H01L214763

    CPC分类号： H01L21/28105 ,  H01L21/28123 ,  H01L21/28247 ,  H01L21/31662

    摘要： A method for forming gate structures with smooth sidewalls by amorphizing the polysilicon along the gate boundaries is described. This method results in minimal gate depletion effects and improved critical dimension control in the gates of smaller devices. The method involves providing a gate silicon oxide layer on the surface of the semiconductor substrate. A gate electrode layer, such as polysilicon is deposited over the gate silicon oxide followed by a masking oxide layer deposited over the gate electrode layer. The masking oxide layer is patterned for the formation of the gate electrode. An ion implantation of silicon or germanium amorphizes the area of the polysilicon not protected by the masking oxide mask and also amorphizes the area along the boundaries of the polysilicon gate. Thereafter, the amorphized silicon is then removed by an anisotropic etch leaving a narrow area of amorphized silicon on the gate electrode sidewalls under the edges of the masking oxide mask completing the gate structure having smooth sidewalls.

    摘要翻译： 描述了通过沿着栅极边界使多晶硅非晶化来形成具有平滑侧壁的栅极结构的方法。 这种方法导致最小的栅极耗尽效应和较小器件的栅极中的改进的临界尺寸控制。 该方法包括在半导体衬底的表面上提供栅极氧化硅层。 在栅极氧化硅上沉积诸如多晶硅的栅极电极层，随后沉积在栅极电极层上的掩模氧化物层。 图案化掩模氧化物层以形成栅电极。 硅或锗的离子注入对未被掩模氧化物掩模保护的多晶硅区域进行非晶化，并且使沿多晶硅栅极边界的区域非晶化。 此后，通过各向异性蚀刻去除非晶化硅，在掩模氧化物掩模的边缘下方的栅极电极侧壁上留下非晶形硅的窄区域，从而完成具有平滑侧壁的栅极结构。

    Method of making direct contact on gate by using dielectric stop layer
    48.
    发明申请
    Method of making direct contact on gate by using dielectric stop layer 有权
    通过使用介电阻挡层在栅极上直接接触的方法

    公开(公告)号：US20050136573A1

    公开(公告)日：2005-06-23

    申请号：US11045958

    申请日：2005-01-28

    申请人： Purakh Rajverma ,  Sanford Chu ,  Lap Chan ,  Yelehanka Ramachandramurthy Pradeep ,  Kai Shao ,  Jia Zheng

    发明人： Purakh Rajverma ,  Sanford Chu ,  Lap Chan ,  Yelehanka Ramachandramurthy Pradeep ,  Kai Shao ,  Jia Zheng

    IPC分类号： H01L21/00 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/768 ,  H01L21/84 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L21/76802 ,  H01L21/76829

    摘要： A CMOS RF device and a method to fabricate said device with low gate contact resistance are described. Conventional MOS transistor is first formed with isolation regions, poly-silicon gate structure, sidewall spacers around poly gate, and implanted source/drain with lightly and heavily doped regions. A silicon dioxide layer such as TEOS is deposited, planarized with chemical mechanical polishing (CMP) to expose the gate and treated with dilute HF etchant to recess the silicon dioxide layer below the surface of the gate. Silicon nitride is then deposited and planarized with CMP and then etched except around the gates, using a oversize poly-silicon gate mask. Inter-level dielectric mask is then deposited, contact holes etched, and contact metal is deposited to form the transistor. During contact hole etch over poly-silicon gate, silicon nitride around the poly gate acts as an etch stop. Resulting structure with direct gate contact achieves significantly reduced gate resistance and thereby improved noise performance at high frequency operation, increased unit power gain frequency (fmax), and reduced gate delay.

    摘要翻译： 描述CMOS RF器件和制造具有低栅极接触电阻的所述器件的方法。 传统的MOS晶体管首先形成有隔离区域，多晶硅栅极结构，围绕多晶硅栅极的侧壁隔离物以及具有轻掺杂和重掺杂区域的注入源极/漏极。 沉积诸如TEOS的二氧化硅层，通过化学机械抛光（CMP）平坦化以暴露栅极，并用稀的HF蚀刻剂处理以使位于栅极表面下方的二氧化硅层凹陷。 然后将氮化硅沉积并用CMP平坦化，然后使用超大型多晶硅栅极掩模在栅极周围进行蚀刻。 然后沉积层间电介质掩模，蚀刻接触孔，并沉积接触金属以形成晶体管。 在多晶硅栅极的接触孔蚀刻期间，多晶硅周围的氮化硅作为蚀刻停止。 具有直接栅极接触的所得结构实现了显着降低的栅极电阻，从而改善了高频操作下的噪声性能，增加的单位功率增益频率（f max）和减小的栅极延迟。

    Method of forming an inductor with continuous metal deposition
    49.
    发明申请
    Method of forming an inductor with continuous metal deposition 审中-公开
    形成具有连续金属沉积的电感器的方法

    公开(公告)号：US20050124131A1

    公开(公告)日：2005-06-09

    申请号：US11034932

    申请日：2005-01-13

    申请人： Chit Hweing ,  Lap Chan ,  Purakh Verma ,  Yelehanka Ramachandramurthy Pradeep ,  Sanford Chu

    发明人： Chit Hweing ,  Lap Chan ,  Purakh Verma ,  Yelehanka Ramachandramurthy Pradeep ,  Sanford Chu

    IPC分类号： H01F17/00 ,  H01L21/02 ,  H01L23/522 ,  H01L21/20 ,  H01L29/00

    CPC分类号： H01L28/10 ,  H01F17/0006 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method is described to fabricate RF inductor devices on a silicon substrate. Low-k or other dielectric material is deposited and patterned to form inductor lower plate trenches. Trenches are lined with barrier film such as TaN, filled with copper, and excess metal planarized using chemical mechanical polishing (CMP). Second layer of a dielectric material is deposited and patterned to form via-hole/trenches. Via-hole/trench patterns are filled with barrier material, and the dielectric film in between the via-hole/trenches is etched to form a second set of trenches. These trenches are filled with copper and planarized. A third layer of a dielectric film is deposited and patterned to form via-hole/trenches. Via-hole/trenches are then filled with barrier material, and the dielectric film between via-hole/trench patterns etched to form a third set of trenches. These trenches are filled with copper metal and excess metal removed by CMP to form said RF inductor.

    摘要翻译： 描述了在硅衬底上制造RF电感器件的方法。 沉积低k或其他电介质材料并图案化以形成电感器下板沟槽。 沟槽衬有阻挡膜，如填充有铜的TaN和使用化学机械抛光（CMP）平坦化的多余金属。 介电材料的第二层被沉积并图案化以形成通孔/沟槽。 通孔/沟槽图案填充有阻挡材料，蚀刻通孔/沟槽之间的电介质膜以形成第二组沟槽。 这些沟槽用铜填充并平坦化。 电介质膜的第三层被沉积并图案化以形成通孔/沟槽。 然后用阻挡材料填充通孔/沟槽，蚀刻通孔/沟槽图案之间的电介质膜以形成第三组沟槽。 这些沟槽填充有铜金属，并通过CMP去除多余的金属以形成所述RF电感器。