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89 条记录 (耗时 0.036 秒)

    SOI device with embedded liner in box layer to limit STI recess
    43.
    发明授权
    SOI device with embedded liner in box layer to limit STI recess 有权
    具有嵌入式衬垫的SOI器件，用于限制STI凹陷

    公开(公告)号：US08987070B2

    公开(公告)日：2015-03-24

    申请号：US13611182

    申请日：2012-09-12

    申请人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth

    发明人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth

    IPC分类号： H01L21/00 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786

    CPC分类号： H01L27/1203 ,  H01L21/31144 ,  H01L21/76283 ,  H01L21/84 ,  H01L29/06 ,  H01L29/66772 ,  H01L29/78654

    摘要： A semiconductor substrate having an isolation region and method of forming the same. The method includes the steps of providing a substrate having a substrate layer, a buried oxide (BOX), a silicon on insulator (SOI) layer, a pad oxide layer, and a pad nitride layer, forming a shallow trench region, etching the pad oxide layer to form ears and etching the BOX layer to form undercuts, depositing a liner on the shallow trench region, depositing a soft mask over the surface of the shallow trench region, filling the shallow trench region, etching the soft mask so that it is recessed to the top of the BOX layer, etching the liner off certain regions, removing the soft mask, and filling and polishing the shallow trench region. The liner prevents shorting of the semiconductor device when the contacts are misaligned.

    摘要翻译： 具有隔离区域的半导体基板及其形成方法。 该方法包括以下步骤：提供具有衬底层，掩埋氧化物（BOX），绝缘体上硅（SOI）层，衬垫氧化物层和衬垫氮化物层的衬底，形成浅沟槽区，蚀刻衬垫 氧化层以形成耳朵并蚀刻BOX层以形成底切，在浅沟槽区域上沉积衬垫，在浅沟槽区域的表面上沉积软掩模，填充浅沟槽区域，蚀刻软掩模，使得它 凹陷到BOX层的顶部，在某些区域蚀刻衬垫，去除软掩模，以及填充和抛光浅沟槽区域。 当触点不对准时，衬垫防止半导体器件的短路。

    Suspended nanowire structure
    44.
    发明授权
    Suspended nanowire structure 有权
    悬浮纳米线结构

    公开(公告)号：US08889564B2

    公开(公告)日：2014-11-18

    申请号：US13600324

    申请日：2012-08-31

    申请人： Kangguo Cheng ,  James J. Demarest ,  Balasubramanian S. Haran

    发明人： Kangguo Cheng ,  James J. Demarest ,  Balasubramanian S. Haran

    IPC分类号： H01L21/302 ,  H01L21/461

    CPC分类号： H01L29/775 ,  B82Y10/00 ,  B82Y40/00 ,  B82Y99/00 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/3086 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/78696 ,  Y10S977/938

    摘要： A mandrel having vertical planar surfaces is formed on a single crystalline semiconductor layer. An epitaxial semiconductor layer is formed on the single crystalline semiconductor layer by selective epitaxy. A first spacer is formed around an upper portion of the mandrel. The epitaxial semiconductor layer is vertically recessed employing the first spacers as an etch mask. A second spacer is formed on sidewalls of the first spacer and vertical portions of the epitaxial semiconductor layer. Horizontal bottom portions of the epitaxial semiconductor layer are etched from underneath the vertical portions of the epitaxial semiconductor layer to form a suspended ring-shaped semiconductor fin that is attached to the mandrel. A center portion of the mandrel is etched employing a patterned mask layer that covers two end portions of the mandrel. A suspended semiconductor fin is provided, which is suspended by a pair of support structures.

    摘要翻译： 具有垂直平面的心轴形成在单晶半导体层上。 通过选择性外延在单晶半导体层上形成外延半导体层。 围绕心轴的上部形成第一间隔件。 使用第一间隔物作为蚀刻掩模，外延半导体层垂直凹入。 在第一间隔物的侧壁和外延半导体层的垂直部分上形成第二间隔物。 从外延半导体层的垂直部分的下方蚀刻外延半导体层的水平底部部分，以形成附接到心轴的悬挂的环形半导体鳍片。 使用覆盖心轴的两个端部的图案化掩模层来蚀刻心轴的中心部分。 提供悬挂的半导体鳍片，其由一对支撑结构悬挂。

    FinFET diode with increased junction area
    46.
    发明授权
    FinFET diode with increased junction area 失效
    FinFET二极管具有增加的接合面积

    公开(公告)号：US08592263B2

    公开(公告)日：2013-11-26

    申请号：US13456921

    申请日：2012-04-26

    申请人： Theodorus Eduardus Standaert ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Tenko Yamashita

    发明人： Theodorus Eduardus Standaert ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Tenko Yamashita

    IPC分类号： H01L21/84

    CPC分类号： H01L29/861 ,  H01L21/845 ,  H01L27/0266 ,  H01L29/24 ,  H01L29/267 ,  H01L29/6609 ,  H01L29/785

    摘要： A FinFET diode and method of fabrication are disclosed. In one embodiment, the diode comprises, a semiconductor substrate, an insulator layer disposed on the semiconductor substrate, a first silicon layer disposed on the insulator layer, a plurality of fins formed in a diode portion of the first silicon layer. A region of the first silicon layer is disposed adjacent to each of the plurality of fins. A second silicon layer is disposed on the plurality of fins formed in the diode portion of the first silicon layer. A gate ring is disposed on the first silicon layer. The gate ring is arranged in a closed shape, and encloses a portion of the plurality of fins formed in the diode portion of the first silicon layer.

    摘要翻译： 公开了一种FinFET二极管及其制造方法。 在一个实施例中，二极管包括半导体衬底，设置在半导体衬底上的绝缘体层，设置在绝缘体层上的第一硅层，形成在第一硅层的二极管部分中的多个鳍片。 第一硅层的区域设置成与多个翅片中的每一个相邻。 第二硅层设置在形成在第一硅层的二极管部分中的多个翅片上。 栅极环设置在第一硅层上。 门环布置成闭合形状，并且包围形成在第一硅层的二极管部分中的多个翅片的一部分。

    SUSPENDED NANOWIRE STRUCTURE
    48.
    发明申请
    SUSPENDED NANOWIRE STRUCTURE 有权
    悬挂式纳米结构

    公开(公告)号：US20140061582A1

    公开(公告)日：2014-03-06

    申请号：US13600324

    申请日：2012-08-31

    申请人： Kangguo Cheng ,  James J. Demarest ,  Balasubramanian S. Haran

    发明人： Kangguo Cheng ,  James J. Demarest ,  Balasubramanian S. Haran

    IPC分类号： H01L29/06 ,  H01L21/20 ,  B82Y40/00

    CPC分类号： H01L29/775 ,  B82Y10/00 ,  B82Y40/00 ,  B82Y99/00 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/3086 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/78696 ,  Y10S977/938

    摘要： A mandrel having vertical planar surfaces is formed on a single crystalline semiconductor layer. An epitaxial semiconductor layer is formed on the single crystalline semiconductor layer by selective epitaxy. A first spacer is formed around an upper portion of the mandrel. The epitaxial semiconductor layer is vertically recessed employing the first spacers as an etch mask. A second spacer is formed on sidewalls of the first spacer and vertical portions of the epitaxial semiconductor layer. Horizontal bottom portions of the epitaxial semiconductor layer are etched from underneath the vertical portions of the epitaxial semiconductor layer to form a suspended ring-shaped semiconductor fin that is attached to the mandrel. A center portion of the mandrel is etched employing a patterned mask layer that covers two end portions of the mandrel. A suspended semiconductor fin is provided, which is suspended by a pair of support structures.

    摘要翻译： 具有垂直平面的心轴形成在单晶半导体层上。 通过选择性外延在单晶半导体层上形成外延半导体层。 围绕心轴的上部形成第一间隔件。 使用第一间隔物作为蚀刻掩模，外延半导体层垂直凹入。 在第一间隔物的侧壁和外延半导体层的垂直部分上形成第二间隔物。 从外延半导体层的垂直部分的下方蚀刻外延半导体层的水平底部部分，以形成附接到心轴的悬挂的环形半导体鳍片。 使用覆盖心轴的两个端部的图案化掩模层来蚀刻心轴的中心部分。 提供悬挂的半导体鳍片，其由一对支撑结构悬挂。