公开(公告)号：US09484068B2

公开(公告)日：2016-11-01

申请号：US15045112

申请日：2016-02-16

申请人： Kilopass Technology, Inc.

发明人： Colin Stewart Bill ,  Harry Luan

IPC分类号： G11C11/39 ,  G11C5/06 ,  G11C16/14

CPC分类号： G11C11/39 ,  G11C5/06 ,  G11C5/063 ,  G11C16/0466 ,  G11C16/14 ,  H01L27/1027 ,  H01L29/7404 ,  H01L29/7436 ,  H01L29/792

摘要： An MTP (Many Times Programmable) memory cell for integrated circuit memory arrays is described. The cell includes an MTP device and a thyristor interconnected so that the MTP device triggers the thyristor to turn on during a Read or Verify operation. The difference in threshold voltages between a data memory cell and a reference memory cell is used to determine the information in the data memory cell. Different memory cell structures may be constructed for different memory array requirements.

摘要翻译： 描述了用于集成电路存储器阵列的MTP（许多次可编程）存储器单元。 该单元包括MTP器件和互连的晶闸管，使得MTP器件在读取或验证操作期间触发晶闸管导通。 使用数据存储单元和参考存储单元之间的阈值电压的差来确定数据存储单元中的信息。 可以为不同的存储器阵列要求构建不同的存储器单元结构。

公开(公告)号：US09460771B2

公开(公告)日：2016-10-04

申请号：US14607023

申请日：2015-01-27

申请人： Kilopass Technology, Inc.

发明人： Harry Luan ,  Bruce L. Bateman ,  Valery Axelrad ,  Charlie Cheng ,  Christophe J. Chevallier

IPC分类号： G11C11/39 ,  G11C11/418 ,  G11C11/419 ,  H01L27/11 ,  G11C11/411 ,  G11C11/416

CPC分类号： G11C11/39 ,  G11C5/14 ,  G11C11/34 ,  G11C11/4113 ,  G11C11/416 ,  G11C11/418 ,  G11C11/419 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0821 ,  H01L27/0826 ,  H01L27/1027 ,  H01L27/11 ,  H01L27/1104

摘要： A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with the thyristor in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM cells.

摘要翻译： 基于用于SRAM集成电路的晶闸管的双晶体管存储单元可以以不同的MOS和双极选择晶体管的组合实现，或者不具有选择晶体管，晶闸管在具有浅沟槽隔离的半导体衬底中。 标准CMOS工艺技术可用于制造SRAM单元。

公开(公告)号：US20160093624A1

公开(公告)日：2016-03-31

申请号：US14841140

申请日：2015-08-31

申请人： Kilopass Technology, Inc.

发明人： Harry Luan ,  Bruce L. Bateman ,  Valery Axelrad ,  Charlie Cheng

IPC分类号： H01L27/102 ,  H01L29/66 ,  H01L29/10 ,  H01L21/3205 ,  H01L29/06 ,  H01L21/762 ,  H01L21/324 ,  H01L29/749 ,  H01L29/16

CPC分类号： H01L27/1027 ,  G11C11/39 ,  H01L21/28035 ,  H01L21/321 ,  H01L21/324 ,  H01L21/76224 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/0834 ,  H01L29/1016 ,  H01L29/102 ,  H01L29/16 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/456 ,  H01L29/66356 ,  H01L29/66363 ,  H01L29/749

摘要： A volatile memory array using vertical thyristors is disclosed together with methods of fabricating the array.

摘要翻译： 公开了使用垂直晶闸管的易失性存储器阵列以及制造阵列的方法。

公开(公告)号：US20160093368A1

公开(公告)日：2016-03-31

申请号：US14740186

申请日：2015-06-15

申请人： Kilopass Technology, Inc.

发明人： Harry Luan ,  Bruce L. Bateman ,  Valery Axelrad ,  Charlie Cheng ,  Christophe J. Chevallier

IPC分类号： G11C11/419 ,  G11C11/418

CPC分类号： G11C11/39 ,  G11C5/14 ,  G11C11/34 ,  G11C11/4113 ,  G11C11/416 ,  G11C11/418 ,  G11C11/419 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0821 ,  H01L27/0826 ,  H01L27/1027 ,  H01L27/11 ,  H01L27/1104

摘要： A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with methods of operation. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.

摘要翻译： 基于用于SRAM集成电路的晶闸管的双晶体管存储单元与操作方法一起被描述。 存储器单元可以在具有浅沟槽隔离的半导体衬底中的晶闸管的MOS和双极选择晶体管的不同组合中实现，或者不具有选择晶体管。 标准CMOS工艺技术可用于制造SRAM。

公开(公告)号：US10438952B2

公开(公告)日：2019-10-08

申请号：US15658346

申请日：2017-07-24

申请人： Kilopass Technology, Inc.

发明人： Harry Luan ,  Bruce L. Bateman ,  Valery Axelrad ,  Charlie Cheng

IPC分类号： G11C11/39 ,  H01L27/102 ,  H01L29/749 ,  H01L29/66 ,  H01L29/10 ,  H01L29/16 ,  H01L29/06 ,  H01L21/762 ,  H01L21/324 ,  H01L21/28 ,  H01L21/321 ,  H01L29/45 ,  H01L49/02 ,  H01L29/423 ,  H01L29/08

摘要： A method of writing data into a volatile thyristor memory cell array and maintaining the data with refresh is disclosed.

公开(公告)号：US10020043B2

公开(公告)日：2018-07-10

申请号：US15426909

申请日：2017-02-07

申请人： Kilopass Technology, Inc.

发明人： Harry Luan ,  Bruce L. Bateman ,  Valery Axelrad ,  Charlie Cheng

IPC分类号： G11C11/34 ,  G11C11/39 ,  H01L27/102 ,  H01L29/74

CPC分类号： G11C11/39 ,  H01L27/1027 ,  H01L29/74 ,  H01L29/749

摘要： A volatile memory array using vertical thyristors is disclosed together with methods of operating the array to read data from and write data to the array.

公开(公告)号：US20180130804A1

公开(公告)日：2018-05-10

申请号：US15807536

申请日：2017-11-08

申请人： Kilopass Technology, Inc.

发明人： Harry Luan ,  Valery Axelrad ,  Charlie Cheng

IPC分类号： H01L27/105 ,  H01L27/08 ,  H01L29/06 ,  H01L29/165 ,  H01L29/74 ,  H01L29/66 ,  H01L21/8229 ,  H01L21/762 ,  H01L21/02 ,  H01L21/265

CPC分类号： H01L27/1052 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/76224 ,  H01L21/8229 ,  H01L27/0817 ,  H01L27/1027 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/45 ,  H01L29/66363 ,  H01L29/66378 ,  H01L29/742 ,  H01L29/749

摘要： Memory arrays of vertical thyristor memory cells with SiGe base layers are described. The composition of the SiGe can be constant or varied depending upon the desired characteristics of the memory cells. The memory cells allow a compact structure with desirable low voltage operations.

公开(公告)号：US20170352665A1

公开(公告)日：2017-12-07

申请号：US15349978

申请日：2016-11-11

申请人： Kilopass Technology, Inc.

发明人： Harry Luan ,  Bruce L. Bateman ,  Valery Axelrad ,  Charlie Cheng

IPC分类号： H01L27/102 ,  H01L27/105 ,  H01L29/74 ,  H01L29/423 ,  H01L27/11 ,  H01L27/108

CPC分类号： H01L27/1027 ,  G11C11/39 ,  H01L27/0817 ,  H01L27/1023 ,  H01L27/1052 ,  H01L27/10805 ,  H01L27/11 ,  H01L29/42308 ,  H01L29/74

摘要： A vertical thyristor memory array including: a vertical thyristor memory cell, the vertical thyristor memory cell including: a p+ anode; an n-base located below the p+ anode; a p-base located below the n-base; a n+ cathode located below the p-base; an isolation trench located around the vertical thyristor memory cell; an assist gate located in the isolation trench adjacent the n-base wherein an entire vertical height of the assist gate is positioned within an entire vertical height of the n-base.

公开(公告)号：US09837418B2

公开(公告)日：2017-12-05

申请号：US15283085

申请日：2016-09-30

申请人： Kilopass Technology, Inc.

发明人： Harry Luan ,  Bruce L. Bateman ,  Valery Axelrad ,  Charlie Cheng

IPC分类号： H01L27/102 ,  H01L29/74 ,  H01L29/749 ,  H01L29/66 ,  H01L29/10 ,  H01L29/16 ,  H01L29/06 ,  H01L21/762 ,  H01L21/324 ,  G11C11/39 ,  H01L21/28 ,  H01L21/321 ,  H01L29/45

CPC分类号： H01L27/1027 ,  G11C11/39 ,  H01L21/28035 ,  H01L21/321 ,  H01L21/324 ,  H01L21/76224 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/0834 ,  H01L29/1016 ,  H01L29/102 ,  H01L29/16 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/456 ,  H01L29/66356 ,  H01L29/66363 ,  H01L29/749

摘要： A volatile memory array using vertical thyristors is disclosed together with methods of fabricating the array.

公开(公告)号：US09812454B2

公开(公告)日：2017-11-07

申请号：US15199934

申请日：2016-06-30

申请人： Kilopass Technology, Inc.

发明人： Harry Luan ,  Valery Axelrad ,  Charlie Cheng

IPC分类号： H01L29/74 ,  H01L27/102 ,  H01L23/532 ,  H01L29/45 ,  H01L21/8229 ,  H01L21/285

CPC分类号： H01L27/1027 ,  G11C11/39 ,  H01L21/02271 ,  H01L21/221 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/32053 ,  H01L21/8229 ,  H01L23/53209 ,  H01L23/53242 ,  H01L27/0817 ,  H01L27/1023 ,  H01L27/10802 ,  H01L28/00 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0839 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/456 ,  H01L29/66363 ,  H01L29/74 ,  H01L29/87

摘要： Methods and systems for reducing electrical disturb effects between thyristor memory cells in a memory array are provided. Electrical disturb effects between cells are reduced by using a material having a reduced minority carrier lifetime as a cathode line that is embedded within the array. Disturb effects are also reduced by forming a potential well within a cathode line, or a one-sided potential barrier in a cathode line.