公开(公告)号：US20130140690A1

公开(公告)日：2013-06-06

申请号：US13311692

申请日：2011-12-06

申请人： Yung-Chi Lin ,  Hsin-Yu Chen ,  Wen-Chih Chiou ,  Ku-Feng Yang ,  Tsang-Jiuh Wu ,  Jing-Cheng Lin

发明人： Yung-Chi Lin ,  Hsin-Yu Chen ,  Wen-Chih Chiou ,  Ku-Feng Yang ,  Tsang-Jiuh Wu ,  Jing-Cheng Lin

IPC分类号： H01L23/498 ,  H01L21/768

CPC分类号： H01L23/49827 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/0557 ,  H01L2224/11011 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/1405 ,  H01L2224/14104 ,  H01L2224/73204 ,  H01L2924/01028 ,  H01L2924/0132 ,  H01L2924/067 ,  H01L2924/0705 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00012

摘要： A device includes a substrate having a front side and a backside, a through-via extending from the backside to the front side of the substrate, and a conductive pad on the backside of the substrate and over the through-via. The conductive pad has a substantially planar top surface. A conductive bump has a non-planar top surface over the substantially planar top surface and aligned to the through-via. The conductive bump and the conductive pad are formed of a same material. No interface is formed between the conductive bump and the conductive pad.

公开(公告)号：US09153462B2

公开(公告)日：2015-10-06

申请号：US12964097

申请日：2010-12-09

申请人： Yu-Liang Lin ,  Weng-Jin Wu ,  Jing-Cheng Lin ,  Wen-Chih Chiou

发明人： Yu-Liang Lin ,  Weng-Jin Wu ,  Jing-Cheng Lin ,  Wen-Chih Chiou

IPC分类号： H01L21/687 ,  H01L21/67

CPC分类号： H01L21/67051 ,  H01L21/68728

摘要： A device and system for thin wafer cleaning is disclosed. A preferred embodiment comprises a spin chuck having at least three holding clamps. A thin wafer with a wafer frame is mounted on the spin chuck through a tape layer. When the holding clamps are unlocked, there is no interference with the removal and placement of the wafer frame. On the other hand, when the holding clamps are locked, the holding clamps are brought into contact with the outer edge of the wafer frame so as to prevent the wafer frame from moving laterally. Furthermore, the shape of the holding clamps in a locked position is capable of preventing the wafer frame from moving vertically.

摘要翻译： 公开了用于薄晶片清洁的装置和系统。 优选实施例包括具有至少三个保持夹具的旋转卡盘。 具有晶片框架的薄晶片通过带层安装在旋转卡盘上。 当保持夹具解锁时，不会干扰晶片框架的移除和放置。 另一方面，当保持夹具被锁定时，保持夹具与晶片框架的外边缘接触，以防止晶片框架横向移动。 此外，保持夹具处于锁定位置的形状能够防止晶片框架垂直移动。

公开(公告)号：US20120145204A1

公开(公告)日：2012-06-14

申请号：US12964097

申请日：2010-12-09

申请人： Yu-Liang Lin ,  Weng-Jin Wu ,  Jing-Cheng Lin ,  Wen-Chih Chiou

发明人： Yu-Liang Lin ,  Weng-Jin Wu ,  Jing-Cheng Lin ,  Wen-Chih Chiou

IPC分类号： B08B3/08 ,  B08B3/02

CPC分类号： H01L21/67051 ,  H01L21/68728

摘要： A device and system for thin wafer cleaning is disclosed. A preferred embodiment comprises a spin chuck having at least three holding clamps. A thin wafer with a wafer frame is mounted on the spin chuck through a tape layer. When the holding clamps are unlocked, there is no interference with the removal and placement of the wafer frame. On the other hand, when the holding clamps are locked, the holding clamps are brought into contact with the outer edge of the wafer frame so as to prevent the wafer frame from moving laterally. Furthermore, the shape of the holding clamps in a locked position is capable of preventing the wafer frame from moving vertically.

摘要翻译： 公开了用于薄晶片清洁的装置和系统。 优选实施例包括具有至少三个保持夹具的旋转卡盘。 具有晶片框架的薄晶片通过带层安装在旋转卡盘上。 当保持夹具解锁时，不会干扰晶片框架的移除和放置。 另一方面，当保持夹具被锁定时，保持夹具与晶片框架的外边缘接触，以防止晶片框架横向移动。 此外，保持夹具处于锁定位置的形状能够防止晶片框架垂直移动。

公开(公告)号：US08853830B2

公开(公告)日：2014-10-07

申请号：US12178021

申请日：2008-07-23

申请人： Hung-Pin Chang ,  Weng-Jin Wu ,  Wen-Chih Chiou ,  Chen-Hua Yu

发明人： Hung-Pin Chang ,  Weng-Jin Wu ,  Wen-Chih Chiou ,  Chen-Hua Yu

IPC分类号： H01L21/768 ,  H01L23/538 ,  H01L25/00 ,  H01L23/48 ,  H01L25/065

CPC分类号： H01L25/0657 ,  H01L21/768 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/13 ,  H01L25/50 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13184 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor substrate structure for use in a semiconductor substrate stack system is presented. The method includes a semiconductor substrate which includes a front-face, a backside, a bulk layer, an interconnect layer that includes a plurality of inter-metal dielectric layers sandwiched between conductive layers, a contact layer that is between the bulk layer and the interconnect layer, and a TSV structure commencing between the bulk layer and the contact layer and terminating at the backside of the substrate. The TSV structure is electrically coupled to the interconnect layer and the TSV structure is electrically coupled to a bonding pad on the backside.

摘要翻译： 本发明提供一种制造用于半导体衬底叠层系统的半导体衬底结构的方法。 该方法包括半导体衬底，其包括前表面，背面，体层，互连层，其包括夹在导电层之间的多个金属间介电层，位于体层和互连之间的接触层 层，以及从本体层和接触层之间开始并终止于衬底背面的TSV结构。 TSV结构电耦合到互连层，并且TSV结构电耦合到背面的接合焊盘。

公开(公告)号：US08387674B2

公开(公告)日：2013-03-05

申请号：US12054097

申请日：2008-03-24

申请人： Chen-Hua Yu ,  Jui-Pin Hung ,  Weng-Jin Wu ,  Jean Wang ,  Wen-Chih Chiou

发明人： Chen-Hua Yu ,  Jui-Pin Hung ,  Weng-Jin Wu ,  Jean Wang ,  Wen-Chih Chiou

IPC分类号： B29C65/00

CPC分类号： H01L25/50 ,  H01L21/67051 ,  H01L24/28 ,  H01L24/75 ,  H01L24/83 ,  H01L24/94 ,  H01L2224/8301 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01094 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/19042 ,  Y10T156/14 ,  H01L2924/00

摘要： The present disclosure provides a bonding apparatus. The bonding apparatus includes a cleaning module designed for cleaning chips; and a chip-to-wafer bonding chamber configured to receive the chips from the cleaning module and designed for bonding the chips to a wafer.

公开(公告)号：US20100144068A1

公开(公告)日：2010-06-10

申请号：US12329304

申请日：2008-12-05

申请人： Wen-Chih Chiou ,  Weng-Jin Wu ,  Chen-Hua Yu

发明人： Wen-Chih Chiou ,  Weng-Jin Wu ,  Chen-Hua Yu

IPC分类号： H01L21/98

CPC分类号： H01L25/0657 ,  H01L25/50 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541

摘要： A method of forming integrated circuits includes providing a wafer that includes a plurality of dies; aligning a first top die to a first bottom die in the wafer; recording a first destination position of the first top die after the first top die is aligned to the first bottom die; bonding the first top die onto the first bottom die; calculating a second destination position of a second top die using the first destination position; moving the second top die to the second destination position; and bonding the second top die onto a second bottom die without any additional alignment action.

摘要翻译： 一种形成集成电路的方法包括提供包括多个管芯的晶片; 将第一顶模与所述晶片中的第一底模对准; 在所述第一顶模与所述第一底模对准之后，记录所述第一顶模的第一目的位置; 将第一顶模连接到第一底模上; 使用所述第一目的地位置计算第二顶模的第二目的位置; 将第二顶部模具移动到第二目的地位置; 以及将所述第二顶模连接到第二底模上而没有任何附加的对准作用。

公开(公告)号：US08528802B2

公开(公告)日：2013-09-10

申请号：US12204063

申请日：2008-09-04

申请人： Chen-Hua Yu ,  Wen-Chih Chiou ,  Weng-Jin Wu

发明人： Chen-Hua Yu ,  Wen-Chih Chiou ,  Weng-Jin Wu

IPC分类号： B23K1/06 ,  B23K31/02

CPC分类号： H01L24/64 ,  B23K1/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/056 ,  H01L2224/75 ,  H01L2224/751 ,  H01L2224/75301 ,  H01L2224/81011 ,  H01L2224/81054 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/30105 ,  Y10T29/53174 ,  H01L2924/00014

摘要： An apparatus including a bond head, a supplemental support, a reduction module, and a transducer is provided. The bond head holds a first substrate that contains a first set of metal pads. The supplemental support holds a second substrate that contains a second set of metal pads. The aligner forms an aligned set of metal pads by aligning the first substrate to the second substrate. The reduction module contains the aligned substrates and a reduction gas flows into the reduction module. The transducer provides repeated relative motion to the aligned set of metal pads.

摘要翻译： 提供了一种包括接合头，补充支撑，还原模块和换能器的装置。 结合头保持包含第一组金属垫的第一衬底。 补充支撑件保持包含第二组金属垫的第二基底。 对准器通过将第一衬底与第二衬底对准而形成对准的一组金属衬垫。 还原模块包含对准的基板，并且还原气体流入还原模块。 传感器向对准的一组金属焊盘提供重复的相对运动。

公开(公告)号：US08344513B2

公开(公告)日：2013-01-01

申请号：US12631172

申请日：2009-12-04

申请人： Chen-Hua Yu ,  Wen-Chih Chiou ,  Weng-Jin Wu

发明人： Chen-Hua Yu ,  Wen-Chih Chiou ,  Weng-Jin Wu

IPC分类号： H01L23/522 ,  H01L21/4763

CPC分类号： H01L21/76846 ,  H01L21/76847 ,  H01L21/76898 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/0557 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2224/05552 ,  H01L2924/00

摘要： A system and a method for protecting through-silicon vias (TSVs) is disclosed. An embodiment comprises forming an opening in a substrate. A liner is formed in the opening and a barrier layer comprising carbon or fluorine is formed along the sidewalls and bottom of the opening. A seed layer is formed over the barrier layer, and the TSV opening is filled with a conductive filler. Another embodiment includes a barrier layer formed using atomic layer deposition.

摘要翻译： 公开了一种用于保护硅通孔（TSV）的系统和方法。 一个实施例包括在衬底中形成开口。 在开口中形成衬垫，并且沿着开口的侧壁和底部形成包含碳或氟的阻挡层。 在阻挡层上形成种子层，并且用导电填料填充TSV开口。 另一实施例包括使用原子层沉积形成的阻挡层。

公开(公告)号：US07960290B2

公开(公告)日：2011-06-14

申请号：US11799637

申请日：2007-05-02

申请人： Chen-Hua Yu ,  Wen-Chih Chiou ,  Weng-Jin Wu

发明人： Chen-Hua Yu ,  Wen-Chih Chiou ,  Weng-Jin Wu

IPC分类号： H01L23/522

CPC分类号： H01L23/5222 ,  H01L21/76224 ,  H01L21/7682 ,  H01L21/76898 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating a semiconductor device. A preferred embodiment comprises forming a via in a semiconductor substrate, filling the via with a disposable material such as amorphous carbon, forming a dielectric layer on the substrate covering the via, performing a back side etch to expose the disposable material in the via. A back side dielectric layer is then depositing, covering the exposed via. A small opening is then formed, and the disposable material is removed, for example by an isotropic etch process. The via may now be filled with a metal and used as a conductor or a dielectric material. The via may also be left unfilled to be used as an air gap.

摘要翻译： 一种半导体器件的制造方法。 优选实施例包括在半导体衬底中形成通孔，用诸如无定形碳的一次性材料填充通孔，在覆盖通孔的衬底上形成电介质层，进行背面蚀刻以暴露通孔中的一次性材料。 然后沉积背面电介质层，覆盖暴露的通孔。 然后形成小的开口，并且例如通过各向同性蚀刻工艺去除一次性材料。 通孔现在可以填充金属并用作导体或电介质材料。 通孔也可以不填充以用作气隙。

公开(公告)号：US07939941B2

公开(公告)日：2011-05-10

申请号：US11769559

申请日：2007-06-27

申请人： Wen-Chih Chiou ,  Chen-Hua Yu ,  Weng-Jin Wu

发明人： Wen-Chih Chiou ,  Chen-Hua Yu ,  Weng-Jin Wu

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541

摘要： The formation of through silicon vias (TSVs) in an integrated circuit (IC) die or wafer is described in which the TSV is formed in the integration process prior to contact or metallization processing. Contacts and bonding pads may then be fabricated after the TSVs are already in place, which allows the TSV to be more dense and allows more freedom in the overall TSV design. By providing a denser connection between TSVs and bonding pads, individual wafers and dies may be bonded directly at the bonding pads. The conductive bonding material, thus, maintains an electrical connection to the TSVs and other IC components through the bonding pads.

摘要翻译： 描述了在集成电路（IC）管芯或晶片中形成通孔硅通孔（TSV），其中在接触或金属化处理之前的集成工艺中形成TSV。 然后可以在TSV已经就位之后制造触点和接合焊盘，这允许TSV更致密并且允许TSV设计中的更多自由度。 通过在TSV和接合焊盘之间提供更密集的连接，单个晶片和管芯可以直接接合在接合焊盘处。 因此，导电接合材料通过接合焊盘保持与TSV和其它IC部件的电连接。