公开(公告)号：US20230378121A1

公开(公告)日：2023-11-23

申请号：US18318836

申请日：2023-05-17

申请人： Tokyo Electron Limited

发明人： Yuhei Matsuo

IPC分类号： H01L23/00 ,  H04N23/56 ,  H04N23/90 ,  G06T7/73 ,  G06T7/00 ,  H04N23/10 ,  G06T7/90

CPC分类号： H01L24/75 ,  H01L24/94 ,  H01L24/83 ,  H04N23/56 ,  H04N23/90 ,  G06T7/73 ,  G06T7/0004 ,  H04N23/10 ,  G06T7/90 ,  H01L24/32 ,  H01L24/29 ,  H01L2224/29186 ,  H01L2924/0544 ,  H01L2924/0504 ,  H01L2924/059 ,  H01L2224/94 ,  H01L2224/32145 ,  H01L2224/75701 ,  H01L2224/75702 ,  H01L2224/75744 ,  H01L2224/75745 ,  H01L2224/75753 ,  H01L2224/7598 ,  H01L2224/8313 ,  H01L2224/8316 ,  H01L2224/83896 ,  H01L2224/8301 ,  H01L2224/7501 ,  G06T2207/30204 ,  G06T2207/30148 ,  G06T2207/10024 ,  G06T2207/10152

摘要： A bonding apparatus bonds a first substrate having a first alignment mark and a second substrate having a second alignment mark. A first radiation unit radiates white light to an imaging area of a first imaging unit when the second alignment mark is imaged by the first imaging unit. A second radiation unit radiates white light to an imaging area of a second imaging unit when the first alignment mark is imaged by the second imaging unit. A controller detects positions of the first alignment mark and the second alignment mark by processing images obtained by the first imaging unit and the second imaging unit, corrects the detected position of the first alignment mark based on a relationship between a wavelength and an intensity of reflection light reflected from the first substrate, and controls a moving unit based on the corrected position of the first alignment mark.

公开(公告)号：US20180013260A1

公开(公告)日：2018-01-11

申请号：US15205789

申请日：2016-07-08

申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

发明人： XUE HUANG ,  DI LIANG

IPC分类号： H01S5/026 ,  H01S5/22 ,  H01S5/02 ,  H01L23/00

CPC分类号： H01S5/026 ,  H01L24/27 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/27452 ,  H01L2224/32145 ,  H01L2224/32505 ,  H01L2224/8301 ,  H01L2924/0533 ,  H01L2924/0534 ,  H01L2924/05341 ,  H01L2924/05342 ,  H01L2924/3641 ,  H01S5/021 ,  H01S5/1032 ,  H01S5/22

摘要： An example device in accordance with an aspect of the present disclosure includes a first layer and a second layer to be bonded to the first layer. The first and second layers are materials that generate gas byproducts when bonded, and the first and/or second layers is/are compatible with photonic device operation based on a separation distance. At least one bonding interface layer is to establish the separation distance for photonic device operation, and is to prevent gas trapping and to facilitate bonding between the first layer and the second layer.

公开(公告)号：US20160322328A1

公开(公告)日：2016-11-03

申请号：US15205346

申请日：2016-07-08

申请人： ZIPTRONIX, INC.

发明人： Qin-Yi Tong ,  Gaius Gillman Fountain, JR. ,  Paul M. Enquist

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC分类号： H01L24/83 ,  H01L21/0206 ,  H01L21/2007 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/322 ,  H01L21/76251 ,  H01L24/26 ,  H01L24/75 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/085 ,  H01L29/06 ,  H01L29/16 ,  H01L2224/8301 ,  H01L2224/8303 ,  H01L2224/83031 ,  H01L2224/8309 ,  H01L2224/83099 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2224/83894 ,  H01L2224/83896 ,  H01L2224/83948 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0106 ,  H01L2924/01061 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01084 ,  H01L2924/01093 ,  H01L2924/0132 ,  H01L2924/05442 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  Y10S148/012 ,  Y10S438/974 ,  Y10T156/10 ,  Y10T156/1043 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01049 ,  H01L2924/01031 ,  H01L2924/3512 ,  H01L2924/00

摘要： A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.

公开(公告)号：US20150303263A1

公开(公告)日：2015-10-22

申请号：US14754111

申请日：2015-06-29

申请人： Ziptronix, Inc.

发明人： Qin-Yi Tong ,  Gaius Gillman Fountain, JR. ,  Paul M. Enquist

IPC分类号： H01L29/16 ,  H01L27/085 ,  H01L29/06

CPC分类号： H01L24/83 ,  H01L21/0206 ,  H01L21/2007 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/322 ,  H01L21/76251 ,  H01L24/26 ,  H01L24/75 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/085 ,  H01L29/06 ,  H01L29/16 ,  H01L2224/8301 ,  H01L2224/8303 ,  H01L2224/83031 ,  H01L2224/8309 ,  H01L2224/83099 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2224/83894 ,  H01L2224/83896 ,  H01L2224/83948 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0106 ,  H01L2924/01061 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01084 ,  H01L2924/01093 ,  H01L2924/0132 ,  H01L2924/05442 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  Y10S148/012 ,  Y10S438/974 ,  Y10T156/10 ,  Y10T156/1043 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01049 ,  H01L2924/01031 ,  H01L2924/3512 ,  H01L2924/00

摘要： A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.

公开(公告)号：US20150287696A1

公开(公告)日：2015-10-08

申请号：US14420181

申请日：2013-03-11

申请人： PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

发明人： Mitsuhiko Ueda ,  Yoshiharu Sanagawa ,  Takanori Aketa ,  Shintaro Hayashi

IPC分类号： H01L23/00

CPC分类号： H01L24/97 ,  B23K20/00 ,  H01L21/52 ,  H01L21/6836 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/75 ,  H01L24/83 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/04026 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/2745 ,  H01L2224/2746 ,  H01L2224/29011 ,  H01L2224/29012 ,  H01L2224/29013 ,  H01L2224/2908 ,  H01L2224/29082 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/3003 ,  H01L2224/32225 ,  H01L2224/32227 ,  H01L2224/32501 ,  H01L2224/32505 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/75252 ,  H01L2224/75301 ,  H01L2224/75744 ,  H01L2224/75745 ,  H01L2224/75753 ,  H01L2224/75901 ,  H01L2224/7598 ,  H01L2224/8301 ,  H01L2224/83013 ,  H01L2224/83065 ,  H01L2224/83075 ,  H01L2224/8309 ,  H01L2224/83123 ,  H01L2224/83127 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83207 ,  H01L2224/83805 ,  H01L2224/83825 ,  H01L2224/8383 ,  H01L2224/83906 ,  H01L2224/83907 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/10161 ,  H01L2924/10162 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1461 ,  H01L2224/83 ,  H01L2924/0105 ,  H01L2924/00014 ,  H01L2924/01032 ,  H01L2924/01083 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2924/00

摘要： A mounting method of mounting chips on a substrate includes a temporarily-bonding process, and a main-bonding process. Temporarily-bonding process is to perform a first basic process, repeatedly depending on the number of the chips. First basic process includes a first step and a second step. First step is to align, on a first metal layer of the substrate, a second metal layer of each chip. Second step is to temporarily bond each chip by subjecting the first and second metal layers to solid phase diffusion bonding. Main-bonding process is to perform a second basic process, repeatedly depending on the number of the chips. Second basic process includes a third step and a fourth step. Third step is to recognize a position of each chip temporarily mounted on the substrate. Fourth step is to firmly bond each chip by subjecting the first and second metal layers to liquid phase diffusion bonding.

摘要翻译： 将芯片安装在基板上的安装方法包括临时粘合工艺和主要粘结工艺。 暂时粘接过程是根据芯片的数量重复执行第一个基本过程。 第一基本过程包括第一步骤和第二步骤。 第一步是在衬底的第一金属层上对准每个芯片的第二金属层。 第二步是通过使第一和第二金属层进行固相扩散接合来临时粘合每个芯片。 主键合过程是根据芯片的数量重复执行第二个基本过程。 第二基本过程包括第三步骤和第四步骤。 第三步是识别临时安装在基板上的每个芯片的位置。 第四步是通过使第一和第二金属层进行液相扩散接合来牢固地结合每个芯片。

公开(公告)号：US20080063878A1

公开(公告)日：2008-03-13

申请号：US11980415

申请日：2007-10-31

申请人： Qin-Yi Tong ,  Gaius Fountain ,  Paul Enquist

发明人： Qin-Yi Tong ,  Gaius Fountain ,  Paul Enquist

IPC分类号： H01L21/20 ,  B32B9/04

CPC分类号： H01L24/83 ,  H01L21/0206 ,  H01L21/2007 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/322 ,  H01L21/76251 ,  H01L24/26 ,  H01L24/75 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/085 ,  H01L29/06 ,  H01L29/16 ,  H01L2224/8301 ,  H01L2224/8303 ,  H01L2224/83031 ,  H01L2224/8309 ,  H01L2224/83099 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2224/83894 ,  H01L2224/83896 ,  H01L2224/83948 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0106 ,  H01L2924/01061 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01084 ,  H01L2924/01093 ,  H01L2924/0132 ,  H01L2924/05442 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  Y10S148/012 ,  Y10S438/974 ,  Y10T156/10 ,  Y10T156/1043 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01049 ,  H01L2924/01031 ,  H01L2924/3512 ,  H01L2924/00

摘要： A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. One etching process The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.

公开(公告)号：US20080053959A1

公开(公告)日：2008-03-06

申请号：US11980664

申请日：2007-10-31

申请人： Qin-Yi Tong ,  Gaius Fountain ,  Paul Enquist

发明人： Qin-Yi Tong ,  Gaius Fountain ,  Paul Enquist

IPC分类号： C23F1/00 ,  C03B29/00

CPC分类号： H01L24/83 ,  H01L21/0206 ,  H01L21/2007 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/322 ,  H01L21/76251 ,  H01L24/26 ,  H01L24/75 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/085 ,  H01L29/06 ,  H01L29/16 ,  H01L2224/8301 ,  H01L2224/8303 ,  H01L2224/83031 ,  H01L2224/8309 ,  H01L2224/83099 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2224/83894 ,  H01L2224/83896 ,  H01L2224/83948 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0106 ,  H01L2924/01061 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01084 ,  H01L2924/01093 ,  H01L2924/0132 ,  H01L2924/05442 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  Y10S148/012 ,  Y10S438/974 ,  Y10T156/10 ,  Y10T156/1043 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01049 ,  H01L2924/01031 ,  H01L2924/3512 ,  H01L2924/00

摘要： A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. One etching process The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.

摘要翻译： 在低温或室温下接合的方法包括通过清洗或蚀刻进行表面清洁和活化的步骤。 一种蚀刻方法该方法还可以包括除去界面聚合的副产物，以防止反向聚合反应以允许诸如硅，氮化硅和SiO 2的材料的室温化学键合。 要结合的表面被抛光到高度的平滑度和平坦度。 VSE可以使用反应离子蚀刻或湿蚀刻来稍微蚀刻被结合的表面。 表面粗糙度和平面度不会降低，并且可以通过VSE工艺增强。 蚀刻的表面可以在诸如氢氧化铵或氟化铵的溶液中冲洗以促进在表面上形成所需的粘结物质。

公开(公告)号：US09640510B2

公开(公告)日：2017-05-02

申请号：US14787397

申请日：2013-07-05

申请人： EV GROUP E. THALLNER GMBH

发明人： Bernhard Rebhan

IPC分类号： H01L21/00 ,  H01L23/00 ,  H01L21/66

CPC分类号： H01L24/83 ,  H01L22/12 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/743 ,  H01L2223/54426 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03602 ,  H01L2224/03616 ,  H01L2224/0381 ,  H01L2224/05561 ,  H01L2224/05564 ,  H01L2224/05567 ,  H01L2224/05647 ,  H01L2224/061 ,  H01L2224/274 ,  H01L2224/2741 ,  H01L2224/27444 ,  H01L2224/2745 ,  H01L2224/27452 ,  H01L2224/27464 ,  H01L2224/2781 ,  H01L2224/2784 ,  H01L2224/27845 ,  H01L2224/29023 ,  H01L2224/29028 ,  H01L2224/29187 ,  H01L2224/8301 ,  H01L2224/83011 ,  H01L2224/83012 ,  H01L2224/83013 ,  H01L2224/83026 ,  H01L2224/8312 ,  H01L2224/83121 ,  H01L2224/83203 ,  H01L2224/8383 ,  H01L2224/83907 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2924/05442 ,  H01L2224/05552

摘要： A method for bonding of a first, at least partially metallic contact surface of a first substrate to a second, at least partially metallic contact surface of a second substrate, with the following steps, especially the following progression: application of a sacrificial layer which is at least partially, especially predominantly soluble in the material of at least one of the contact surfaces to at least one of the contact surfaces, bonding of the contact surfaces with at least partial solution of the sacrificial layer in at least one of the contact surfaces.

公开(公告)号：US20160086913A1

公开(公告)日：2016-03-24

申请号：US14957501

申请日：2015-12-02

申请人： ZIPTRONIX, INC.

发明人： Qin-Yi Tong ,  Gaius Gillman Fountain, JR. ,  Paul M. Enquist

IPC分类号： H01L23/00

CPC分类号： H01L24/83 ,  H01L21/0206 ,  H01L21/2007 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/322 ,  H01L21/76251 ,  H01L24/26 ,  H01L24/75 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/085 ,  H01L29/06 ,  H01L29/16 ,  H01L2224/8301 ,  H01L2224/8303 ,  H01L2224/83031 ,  H01L2224/8309 ,  H01L2224/83099 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2224/83894 ,  H01L2224/83896 ,  H01L2224/83948 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0106 ,  H01L2924/01061 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01084 ,  H01L2924/01093 ,  H01L2924/0132 ,  H01L2924/05442 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  Y10S148/012 ,  Y10S438/974 ,  Y10T156/10 ,  Y10T156/1043 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01049 ,  H01L2924/01031 ,  H01L2924/3512 ,  H01L2924/00

摘要： A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.

公开(公告)号：US20150364441A1

公开(公告)日：2015-12-17

申请号：US14741181

申请日：2015-06-16

申请人： Skorpios Technologies, Inc.

发明人： Damien Lambert

IPC分类号： H01L23/00

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/30 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0361 ,  H01L2224/04026 ,  H01L2224/05557 ,  H01L2224/05638 ,  H01L2224/1161 ,  H01L2224/13013 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13138 ,  H01L2224/136 ,  H01L2224/14131 ,  H01L2224/29017 ,  H01L2224/29082 ,  H01L2224/29109 ,  H01L2224/3003 ,  H01L2224/3012 ,  H01L2224/32145 ,  H01L2224/32147 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81903 ,  H01L2224/8301 ,  H01L2224/83012 ,  H01L2224/83048 ,  H01L2224/83139 ,  H01L2224/8314 ,  H01L2224/83191 ,  H01L2224/83385 ,  H01L2224/83815 ,  H01L2224/83902 ,  H01L2224/9211 ,  H01L2225/06513 ,  H01L2225/06555 ,  H01L2924/01014 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83

摘要： Micro pillars are formed in silicon. The micro pillars are used in boding the silicon to hetero-material such as III-V material, ceramics, or metals. In bonding the silicon to the hetero-material, indium is used as a bonding material and attached to the hetero-material. The bonding material is heated and the silicon and the hetero-material are pressed together. As the silicon and the hetero-material are pressed together, the micro pillars puncture the bonding material. In some embodiments, pedestals are used in the silicon as hard stops to align the hetero-material with the silicon.

摘要翻译： 微柱形成在硅中。 微柱用于将硅掺入诸如III-V材料，陶瓷或金属的异质材料中。 在将硅键合到异质材料时，使用铟作为结合材料并附着到异质材料上。 加热接合材料，并将硅和异质材料压在一起。 当硅和异质材料被压在一起时，微柱刺穿接合材料。 在一些实施例中，在硅中使用基座作为硬止动器以使异质材料与硅对准。