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    Circuits and methods for matching device characteristics for analog and mixed-signal designs
    41.
    发明授权
    Circuits and methods for matching device characteristics for analog and mixed-signal designs 失效
    用于匹配模拟和混合信号设计的器件特性的电路和方法

    公开(公告)号：US07086020B2

    公开(公告)日：2006-08-01

    申请号：US10733079

    申请日：2003-12-11

    申请人： Howard Hao Chen ,  Louis Lu-Chen Hsu ,  Charlie Chornglii Hwang

    发明人： Howard Hao Chen ,  Louis Lu-Chen Hsu ,  Charlie Chornglii Hwang

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： Circuit designs and methods are provided for matching device characteristics for, e.g., analog or mixed-signal semiconductor integrated circuit designs. In particular, circuit layout patterns and layout methods are provided which enable precise or proportional matching of circuit components by uniformly distributing circuit components in a manner that eliminates or significantly minimizes the sensitivity of such circuit components to environmental effects and process variations, thereby improving the performance of analog and mixed-signal circuits.

    摘要翻译： 提供电路设计和方法用于匹配例如模拟或混合信号半导体集成电路设计的器件特性。 特别地，提供电路布局图案和布局方法，其通过以消除或显着地最小化这些电路部件对环境影响和工艺变化的灵敏度的方式均匀地分配电路部件来实现电路部件的精确或比例匹配，从而提高性能 的模拟和混合信号电路。

    Semiconductor structure having in-situ formed unit resistors
    43.
    发明授权
    Semiconductor structure having in-situ formed unit resistors 有权
    具有原位形成单元电阻器的半导体结构

    公开(公告)号：US06700203B1

    公开(公告)日：2004-03-02

    申请号：US09686742

    申请日：2000-10-11

    申请人： Cyril Cabral, Jr. ,  Lawrence Clevenger ,  Louis Lu-Chen Hsu ,  Keith Kwong Hon Wong

    发明人： Cyril Cabral, Jr. ,  Lawrence Clevenger ,  Louis Lu-Chen Hsu ,  Keith Kwong Hon Wong

    IPC分类号： H01L2348

    CPC分类号： H01L28/20 ,  H01L27/0688

    摘要： An electronic structure that has in-situ formed unit resistors and a method for fabricating such structure are disclosed. The electronic structure that has in-situ formed unit resistors consists of a first plurality of conductive elements formed in an insulating material layer, a plurality of electrically resistive vias formed on top and in electrical communication with at least one of the first plurality of conductive elements, and a second plurality of conductive elements formed on top of and in electrical communication with at least one of the plurality of electrically resistive vias. The present invention novel structure may further be formed in a multi-level configuration such that multi-level resistors may be connected in-series to provide larger resistance values. The present invention novel structure may further be combined with a capacitor network to form desirable RC circuits.

    摘要翻译： 公开了一种具有原位形成的单位电阻器的电子结构及其制造方法。 具有原位形成的单元电阻器的电子结构由形成在绝缘材料层中的第一多个导电元件组成，多个电阻通孔形成在顶部并与第一多个导电元件中的至少一个电连通 以及形成在所述多个电阻通孔中的至少一个上方并与之电气连通的第二多个导电元件。 本发明的新颖结构可以进一步形成为多电平配置，使得多电平电阻器可以串联连接以提供更大的电阻值。 本发明的新颖结构还可以与电容器网络组合以形成期望的RC电路。

    Enhanced bitline equalization for hierarchical bitline architecture
    44.
    发明授权
    Enhanced bitline equalization for hierarchical bitline architecture 有权
    分级位线架构的增强型位线均衡

    公开(公告)号：US06504777B1

    公开(公告)日：2003-01-07

    申请号：US09924661

    申请日：2001-08-08

    申请人： Louis Lu-Chen Hsu ,  Li-Kong Wang

    发明人： Louis Lu-Chen Hsu ,  Li-Kong Wang

    IPC分类号： G11C700

    CPC分类号： G11C7/12 ,  G11C11/4094

    摘要： In a high density dynamic memory circuit, the sense amplifiers are shared by several bitlines in order to maintain a high density and low power design. However, the bitline equalization level drifts after several cycles of operation, caused by an unbalanced capacitance resulting from a size difference of n-FET and p-FET latches in the sense amplifiers. An extra compensating capacitance Ce is added to the NCS node to adjust the loading capacitance to eliminate the bitline drifting.

    摘要翻译： 在高密度动态存储器电路中，读出放大器由几个位线共享，以保持高密度和低功率设计。 然而，由于读出放大器中的n-FET和p-FET锁存器的大小差异导致的不平衡电容引起了几个周期的操作之后，位线均衡电平漂移。 一个额外的补偿电容Ce被添加到NCS节点以调整负载电容以消除位线漂移。

    Defect management engine for semiconductor memories and memory systems
    45.
    发明授权
    Defect management engine for semiconductor memories and memory systems 有权
    半导体存储器和存储器系统的缺陷管理引擎

    公开(公告)号：US6141267A

    公开(公告)日：2000-10-31

    申请号：US243645

    申请日：1999-02-03

    申请人： Toshiaki Kirihata ,  Louis Lu-Chen Hsu ,  Chandrasekhar Narayan

    发明人： Toshiaki Kirihata ,  Louis Lu-Chen Hsu ,  Chandrasekhar Narayan

    IPC分类号： G11C5/02 ,  G11C8/06 ,  G11C11/00 ,  G11C29/00 ,  G11C7/00

    CPC分类号： G11C29/808 ,  G11C11/005 ,  G11C29/846 ,  G11C5/02 ,  G11C8/06

    摘要： A defect management engine (DME) for memories integrates a plurality of redundancy data cells and a plurality of redundancy address cells in the same array. The redundancy data cells are used for replacing defective cells in the memories. The redundancy address cells store the addresses of the defective cells. The memories are preferably sub-divided into a plurality of domains. A plurality of defective cells in each domain are supported by a plurality of repair units, each consisting of one or more redundancy data bits and redundancy address bits in the DME. When one or more data bits are read from a domain in the memory, the corresponding wordline in the DME simultaneously activates a plurality of repair units coupling to the wordline (self-contained domain selection). The redundancy data bits and the redundancy address bits are also read from the redundancy data cells and redundancy address cells, respectively. The DME logic detects whether or not the redundancy address bits match or do not match the address inputs of each repair unit (self contained redundancy match detection). This couples either redundancy data bits from the DME (i.e., a matching condition) or the data bits from the domain in the memories (i.e., a no match condition) to the corresponding DQ (self-contained redundancy replacement). The DME enables an integrated redundancy means (self-contained domain selection, self-contained redundancy match detection, and self-contained redundancy replacement). Single bit replacement, multi-bit replacement, line replacement, and variable bit size replacement are discussed. Finally, an extension of the DME concept to a memory system is also discussed.

    摘要翻译： 用于存储器的缺陷管理引擎（DME）将多个冗余数据单元和多个冗余地址单元集成在相同的阵列中。 冗余数据单元用于替换存储器中的有缺陷的单元。 冗余地址单元存储有缺陷单元的地址。 存储器优选地被细分为多个域。 每个域中的多个缺陷单元由多个修复单元支持，每个修复单元由DME中的一个或多个冗余数据位和冗余地址位组成。 当从存储器中的域读取一个或多个数据位时，DME中的相应字线同时激活耦合到字线（自包含域选择）的多个修复单元。 冗余数据位和冗余地址位也分别从冗余数据单元和冗余地址单元读取。 DME逻辑检测冗余地址位是否匹配或不匹配每个修复单元的地址输入（自包含冗余匹配检测）。 这将来自DME的冗余数据位（即，匹配条件）或来自存储器中的域的数据位（即，不匹配条件）耦合到相应的DQ（独立冗余替换）。 DME可实现集成的冗余手段（自包含域选择，独立冗余匹配检测和自包含冗余替换）。 讨论了单位替换，多位替换，线替换和可变位大小替换。 最后还讨论了将DME概念扩展到内存系统。

    Packing density for flash memories
    46.
    发明授权
    Packing density for flash memories 失效
    闪存的包装密度

    公开(公告)号：US5892257A

    公开(公告)日：1999-04-06

    申请号：US708432

    申请日：1996-09-05

    申请人： Joyce Elizabeth Acocella ,  Carol Galli ,  Louis Lu-Chen Hsu ,  Seiki Ogura ,  Nivo Rovedo ,  Joseph Francis Shepard

    发明人： Joyce Elizabeth Acocella ,  Carol Galli ,  Louis Lu-Chen Hsu ,  Seiki Ogura ,  Nivo Rovedo ,  Joseph Francis Shepard

    IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11546 ,  Y10S148/117 ,  Y10S438/981

    摘要： Improved packing density as well as improved performance and manufacturing yield is achieved in an electrically programmable memory by confining floating gate structures between isolation structures covered with a thin nitride layer. The confinement of the floating gate is achieved by planarization, preferably with a self-limiting chemical/mechanical polishing process, to the surface of the nitride layer covering the isolation structures. Gate oxide and control electrode connections can then be formed on a substantially planar surface without compromising the quality of the gate oxide or breakdown voltage the device must withstand for programming. Since severe topology is avoided over which these connections are formed, improved formation of low resistance connections, possibly including metal connections, are possible and allow scaling of transistors of the memory cells to be scaled to sizes not previously possible.

    摘要翻译： 通过将浮置栅极结构限制在被薄氮化物层覆盖的隔离结构之间，可在电可编程存储器中实现提高的封装密度以及改进的性能和制造产量。 浮栅的限制是通过平面化，优选采用自限制化学/机械抛光工艺，覆盖覆盖隔离结构的氮化物层的表面来实现的。 然后可以在基本平坦的表面上形成栅极氧化物和控制电极连接，而不会损害器件必须承受编程的栅极氧化物的质量或击穿电压。 由于避免了形成这些连接的严格的拓扑结构，所以可能包括可能包括金属连接的低电阻连接的形成得到改进，并且允许将存储器单元的晶体管缩放到先前不可能的尺寸。

    SOI transistor having a self-aligned body contact
    47.
    发明授权
    SOI transistor having a self-aligned body contact 失效
    具有自对准体接触的SOI晶体管

    公开(公告)号：US5729039A

    公开(公告)日：1998-03-17

    申请号：US642834

    申请日：1996-05-03

    申请人： Klaus Dietrich Beyer ,  Taqi Nasser Buti ,  Chang-Ming Hsieh ,  Louis Lu-Chen Hsu

    发明人： Klaus Dietrich Beyer ,  Taqi Nasser Buti ,  Chang-Ming Hsieh ,  Louis Lu-Chen Hsu

    IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L27/12

    CPC分类号： H01L29/66772 ,  H01L29/41783 ,  H01L29/78612 ,  Y10S148/15

    摘要： An SOI transistor has a self-aligned body contact formed through an extension to the gate, thereby forming the body contact with minimal increase in area and also avoiding the need to tie the source to the body, as in prior art schemes that passed the body contact through the source. The body contact aperture is formed by raising the source and drain to define an initial aperture, depositing a conformal layer that is etched to create aperture-defining sidewalls and etching the contact aperture using these sidewalls to define sidewall support members that support insulating sidewalls to isolate the collection electrode from both the gate and from the source and drain.

    摘要翻译： SOI晶体管具有通过到门的延伸形成的自对准体接触，从而以最小的面积增加形成身体接触，并且还避免了将源连接到身体的需要，如通过身体的现有技术方案 通过来源联系。 身体接触孔通过提高源极和漏极以形成初始孔径而形成，沉积被蚀刻以形成孔限定侧壁的共形层并且使用这些侧壁蚀刻接触孔以限定支撑绝缘侧壁以隔离的侧壁支撑构件 收集电极来自闸门和源极和漏极。