中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

58 records (took 0.021 seconds)

    Damascene process of RRAM top electrodes
    44.
    发明授权
    Damascene process of RRAM top electrodes 有权
    RRAM顶电极的镶嵌工艺

    公开(公告)号：US09425391B1

    公开(公告)日：2016-08-23

    申请号：US14638189

    申请日：2015-03-04

    Applicant: Macronix International Co., Ltd.

    Inventor： Erh-Kun Lai ,  Feng-Min Lee ,  Yu-Yu Lin

    IPC: H01L29/02 ,  H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/1253 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1625 ,  H01L45/1633

    Abstract: A method is provided for manufacturing a memory. An insulating layer is formed over an array of interlayer conductors, and etched to define a first opening corresponding to a first interlayer conductor in the array, where the etching stops at a first top surface of the first interlayer conductor. A metal oxide layer is formed on the first top surface. A first layer of barrier material is deposited conformal with and contacting the metal oxide layer and surfaces of the first opening. Subsequently the insulating layer is etched to define a second opening corresponding to a second interlayer conductor in the array, where the etching stops at a second top surface of the second interlayer conductor. A second layer of barrier material is deposited conformal with and contacting the first layer of barrier material in the first opening. The first opening is filled with a conductive material.

    Abstract translation: 提供了一种用于制造存储器的方法。 在层间导体阵列之上形成绝缘层，并蚀刻以形成对应于阵列中的第一层间导体的第一开口，其中蚀刻停止在第一层间导体的第一顶表面处。 金属氧化物层形成在第一顶表面上。 第一层阻挡材料与第一开口的金属氧化物层和表面共形并与其接触。 随后，绝缘层被蚀刻以限定对应于阵列中的第二层间导体的第二开口，其中蚀刻停止在第二层间导体的第二顶表面处。 第二层阻挡材料与第一开口中的第一阻隔材料层共形并与其接触。 第一个开口填充有导电材料。

    MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME
    45.
    发明申请
    MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME 有权
    存储器件及其制造方法

    公开(公告)号：US20160240776A1

    公开(公告)日：2016-08-18

    申请号：US14623654

    申请日：2015-02-17

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Yu-Yu Lin ,  Feng-Min Lee

    IPC: H01L45/00

    CPC classification number: H01L45/124 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1633

    Abstract: A memory device comprises a substrate, a first electrode layer, a spacer, a memory layer and a second electrode layer. The substrate has a recess. The first electrode layer is formed in the recess and has a top surface exposed from an opening of the recess. The spacer covers on a portion of the top surface, so as to define a contact area on the top surface. The memory layer is formed on the contact area. The second electrode layer is formed on the memory layer and electrically connected to the memory layer.

    Abstract translation: 存储器件包括衬底，第一电极层，间隔物，存储层和第二电极层。 基板具有凹部。 第一电极层形成在凹部中并且具有从凹部的开口露出的顶表面。 间隔件覆盖在顶表面的一部分上，以便限定顶表面上的接触区域。 存储层形成在接触区域上。 第二电极层形成在存储层上并与存储层电连接。

    RESISTIVE MEMORY DEVICE WITH RING-SHAPED METAL OXIDE ON TOP SURFACES OF RING-SHAPED METAL LAYER AND BARRIER LAYER
    46.
    发明申请
    RESISTIVE MEMORY DEVICE WITH RING-SHAPED METAL OXIDE ON TOP SURFACES OF RING-SHAPED METAL LAYER AND BARRIER LAYER 有权
    具有环形金属氧化物的环形存储器件在环形金属层和障碍层的顶表面上

    公开(公告)号：US20160225983A1

    公开(公告)日：2016-08-04

    申请号：US14603390

    申请日：2015-01-23

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Yu-Yu Lin ,  Feng-Min Lee ,  Kuang-Hao Chiang ,  Ming-Hsiu Lee

    IPC: H01L45/00

    CPC classification number: H01L45/146 ,  H01L45/04 ,  H01L45/124 ,  H01L45/1633

    Abstract: A resistive memory device is provided, comprising a bottom electrode, a patterned dielectric layer with a via formed on the bottom electrode, a barrier layer formed at sidewalls and a bottom surface of the via as a liner, a ring-shaped metal layer formed at sidewalls and a bottom surface of the barrier layer, and a ring-shaped metal oxide formed on a top surface of the ring-shaped metal layer.

    Abstract translation: 提供了一种电阻式存储器件，包括底部电极，形成在底部电极上的通孔的图案化电介质层，形成在通孔的侧壁和底部表面的阻挡层作为衬垫，形成在环形金属层 侧壁和阻挡层的底表面，以及形成在环形金属层的顶表面上的环形金属氧化物。

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD AND OPERATING METHOD FOR THE SAME
    47.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD AND OPERATING METHOD FOR THE SAME 有权
    半导体器件及其制造方法及其工作方法

    公开(公告)号：US20140160852A1

    公开(公告)日：2014-06-12

    申请号：US13710517

    申请日：2012-12-11

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Feng-Ming Lee ,  Yu-Yu Lin ,  Ming-Hsiu Lee

    IPC: G11C16/04 ,  H01L29/423 ,  H01L29/788

    CPC classification number: G11C16/0408 ,  H01L21/28273 ,  H01L29/788

    Abstract: A semiconductor device and a manufacturing method and an operating method for the same are provided. The semiconductor device comprises a substrate, a doped region and a stack structure. The doped region is in the substrate. The stack structure is on the substrate. The stack structure comprises a dielectric layer, an electrode layer, a solid electrolyte layer and an ion supplying layer.

    Abstract translation: 提供了一种半导体器件及其制造方法及其操作方法。 半导体器件包括衬底，掺杂区域和堆叠结构。 掺杂区域在衬底中。 堆叠结构在衬底上。 堆叠结构包括电介质层，电极层，固体电解质层和离子供给层。

    IN-MEMORY COMPUTATION DEVICE
    48.
    发明申请
    IN-MEMORY COMPUTATION DEVICE 有权

    公开(公告)号：US20240412784A1

    公开(公告)日：2024-12-12

    申请号：US18330369

    申请日：2023-06-07

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Yu-Yu Lin ,  Feng-Min Lee

    IPC: G11C13/00

    Abstract: An in-memory computation device includes multiple computation blocks, a first reference weight block, and an output result generator. The computation blocks have multiple weighting values, receive multiple input signals respectively, and generate multiple computation results. Each of the computation blocks generates each of the computation results according to each of the corresponding input signals and corresponding weighting values. The first reference weight block provides a first reference resistance according to multiple reference weighting values and generates a first reference signal according to the first reference resistance and a read voltage. The output result generator generates multiple output computation results according to the first reference signal and the computation results.

    CACHE DEVICE AND OPERATION METHOD THEREOF
    49.
    发明公开
    CACHE DEVICE AND OPERATION METHOD THEREOF 审中-公开

    公开(公告)号：US20240304238A1

    公开(公告)日：2024-09-12

    申请号：US18180145

    申请日：2023-03-08

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Feng-Min Lee ,  Yu-Yu Lin

    IPC: G11C11/4096 ,  G11C11/4093

    CPC classification number: G11C11/4096 ,  G11C11/4093

    Abstract: The disclosure provides a cache device, which includes: a first transistor having a control terminal, a first terminal, and a second terminal, in which the first terminal of the first transistor is coupled to an input voltage, and the second terminal of the first transistor is coupled to a storage node; an inverter having an input terminal and an output terminal, in which the input terminal is coupled to the storage node; and a second transistor having a control terminal, a first terminal, and a second terminal, in which the first terminal of the second transistor is coupled to the output terminal of the inverter, and the second terminal of the second transistor is configured to output a read voltage.

    ARTIFICIAL NEURAL NETWORK OPERATION CIRCUIT AND IN-MEMORY COMPUTATION DEVICE THEREOF
    50.
    发明公开
    ARTIFICIAL NEURAL NETWORK OPERATION CIRCUIT AND IN-MEMORY COMPUTATION DEVICE THEREOF 审中-公开

    公开(公告)号：US20240282382A1

    公开(公告)日：2024-08-22

    申请号：US18172306

    申请日：2023-02-22

    Applicant: Macronix International Co., Ltd.

    Inventor： Yu-Hsuan Lin ,  Yu-Yu Lin ,  Hsiang-Lan Lung

    IPC: G11C16/12 ,  G11C16/08 ,  G11C16/24

    CPC classification number: G11C16/12 ,  G11C16/08 ,  G11C16/24

    Abstract: An artificial neural network operation circuit and an in-memory computation device of the artificial neural network operation circuit are proposed. The in-memory computation device includes a memory cell array, a compensation memory cell string, and an operator. The memory cell array has a plurality of memory cells to store a plurality of weight values. The memory cell array has a plurality of word lines and a plurality of bit lines. Each compensation memory cell of the compensation memory cell string stores a unit weight value. The operator multiplies a signal on a compensation bit line by peak weight information of the weight values to generate a first signal and adds the first signal to each signal on the bit lines to obtain a plurality of computation results, respectively.

Patent Agency Ranking