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    Methods and systems for improving power delivery and signaling in stacked semiconductor devices
    41.
    发明授权
    Methods and systems for improving power delivery and signaling in stacked semiconductor devices 有权

    公开(公告)号：US10134712B1

    公开(公告)日：2018-11-20

    申请号：US15684703

    申请日：2017-08-23

    Applicant: Micron Technology, Inc.

    Inventor： Anthony D. Veches

    IPC: H01L23/48 ,  H01L25/065 ,  H01L23/64 ,  H01L25/00

    Abstract: Semiconductor die assemblies including stacked semiconductor dies having parallel plate capacitors formed between adjacent pairs of semiconductor dies in the stack, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die and a second semiconductor die stacked over the first semiconductor die. The first semiconductor die includes an upper surface having a first capacitor plate formed thereon, and the second semiconductor die includes a lower surface facing the upper surface of the first semiconductor die and having a second capacitor plate formed thereon. A dielectric material is formed at least partially between the first and second capacitor plates. The first capacitor plate, second capacitor plate, and dielectric material together form a capacitor that stores charge locally within the stack, and that can be accessed by the first and/or second semiconductor dies.

    POWER DISTRIBUTION FOR STACKED MEMORY
    46.
    发明申请
    POWER DISTRIBUTION FOR STACKED MEMORY 有权

    公开(公告)号：US20230090919A1

    公开(公告)日：2023-03-23

    申请号：US17992726

    申请日：2022-11-22

    Applicant: Micron Technology, Inc.

    Inventor： Anthony D. Veches ,  Brian P. Callaway

    IPC: G11C11/4074 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/525 ,  G11C11/22 ,  G06F13/16

    Abstract: Methods, systems, and devices for power distribution for stacked memory are described. A memory die may be configured with one or more conductive paths for providing power to another memory die, where each conductive path may pass through the memory die but may be electrically isolated from circuitry for operating the memory die. Each conductive path may provide an electronic coupling between at least one of a first set of contacts of the memory die (e.g., couplable with a power source) and at least one of a second set of contacts of the memory die (e.g., couplable with another memory die). To support operations of the memory die, a contact of the first set may be coupled with circuitry for operating a memory array of the memory die, and to support operations of another memory die, another contact of the first set may be electrically isolated from the circuitry.

    VOLTAGE REGULATION DISTRIBUTION FOR STACKED MEMORY
    47.
    发明申请
    VOLTAGE REGULATION DISTRIBUTION FOR STACKED MEMORY 有权

    公开(公告)号：US20230046912A1

    公开(公告)日：2023-02-16

    申请号：US17400914

    申请日：2021-08-12

    Applicant: Micron Technology, Inc.

    Inventor： Anthony D. Veches ,  Brian P. Callaway

    IPC: G06F3/06

    Abstract: Methods, systems, and devices for voltage regulation distribution for stacked memory are described. A stacked memory device may support various techniques for coupling between voltage regulation circuitry of multiple memory dies, or for coupling of voltage regulation circuitry of some memory dies with circuitry associated with operating memory arrays of other memory dies. In some examples, such techniques may include cross-coupling of voltage regulation circuitry based on access activity or a degree of access activity for array circuitry. In some examples, such techniques may include isolating voltage regulation circuitry based on access activity or a degree of access activity for array circuitry. Dynamic coupling or isolation between voltage regulation circuitry may be supported by various signaling related to a stacked memory device, such as signaling between the stacked memory dies, signaling between a memory die and a central controller, or signaling between the stacked memory device and a host device.

    Refresh-related activation improvements
    48.
    发明授权
    Refresh-related activation improvements 有权

    公开(公告)号：US11282562B2

    公开(公告)日：2022-03-22

    申请号：US17159706

    申请日：2021-01-27

    Applicant: Micron Technology, Inc.

    Inventor： Stephen Michael Kaminski ,  Anthony D. Veches ,  James S. Rehmeyer ,  Debra M. Bell ,  Dale Herber Hiscock ,  Joshua E. Alzheimer

    IPC: G11C11/406 ,  G11C11/4072 ,  G11C11/4091

    Abstract: Methods, systems, and devices for refresh-related activation in memory are described. A memory device may conduct a refresh operation to preserve the integrity of data. A refresh operation may be associated with a refresh time where the memory device is unable to execute or issue any commands (e.g., access commands). By posting (e.g., saving) one or more commands and/or row addresses during the refresh time, the memory device may be configured to execute the saved commands and/or re-open one or more rows associated with the saved row addresses at a later time (e.g., upon completion of the refresh operation). Accordingly, fewer commands may be issued to activate the memory cells after the refresh time.

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