-
公开(公告)号：US10832779B2
公开(公告)日：2020-11-10
申请号：US16530100
申请日：2019-08-02
Applicant: Micron Technology, Inc.
Inventor： Dheeraj Srinivasan , Jeffrey M. Tsai , Ali Mohammadzadeh , Terry M. Grunzke
Abstract: Apparatuses and methods for an automated dynamic word line start voltage. An example apparatus includes a controller and a memory device. The memory device is configured to maintain, internal to the memory device, a status of a number of open blocks in the memory device. The status can include a programming operation being initiated in the respective number of open blocks. Responsive to receipt of, from the controller, a request to direct initiation of the programming operation to a word line, determine a group of memory cells associated with the word line that programs first relative to other groups of memory cells associated with the word line and maintain, included in the status of an open block, a voltage at which the group of memory cells is the first group to program.
-
公开(公告)号：US10698624B2
公开(公告)日：2020-06-30
申请号：US16178366
申请日：2018-11-01
Applicant: Micron Technology, Inc.
Inventor： Dheeraj Srinivasan , Ali Mohammadzadeh
IPC: G06F3/06 , G11C11/56 , G11C16/10 , G06F12/02 , G06F12/0868 , G06F12/0811
Abstract: Apparatuses and methods for performing buffer operations in memory are provided. An example apparatus can include an array of memory cells, a page buffer, and a controller. The page buffer can be configured to store a number of pages of data in respective caches of the page buffer. The controller can be configured to program the number of pages of data to a first group of cells in the array. The programming operation can include programming the first group of cells to target states encoded with respective data patterns. The programming operation can include incrementally releasing a first of the respective caches of the page buffer responsive to completing programming of cells programmed to a particular first one of the target states.
-
公开(公告)号：US10388379B2
公开(公告)日：2019-08-20
申请号：US15531283
申请日：2017-03-21
Applicant: Micron Technology, Inc.
Inventor： Dheeraj Srinivasan , Jeffrey M. Tsai , Ali Mohammadzadeh , Terry M. Grunzke
Abstract: An apparatus includes a controller and a memory device. The memory device is configured to maintain, internal to the memory device, a status of a number of open blocks in the memory device. The status can include a programming operation being initiated in the respective number of open blocks. Responsive to receipt of, from the controller, a request to direct initiation of the programming operation to a word line, determine a group of memory cells associated with the word line that programs first relative to other groups of memory cells associated with the word line and maintain, included in the status of an open block, a voltage at which the group of memory cells is the first group to program.
-
公开(公告)号：US20190155744A1
公开(公告)日：2019-05-23
申请号：US15819941
申请日：2017-11-21
Applicant: Micron Technology, Inc.
Inventor： Dheeraj Srinivasan , Ali Mohammadzadeh , Michael G. Miller , Xiaoxiao Zhang , Jung Sheng Hoei
IPC: G06F12/1009
Abstract: An example method of the present disclosure includes, responsive to a loss of last written page information by a memory system, initiating a last written page search to determine last written page information of a memory device, where the last written page search is initiated via a command from a controller of the memory system to the memory device, responsive to receiving the command, performing the last written page search on the memory device, and providing the last written page information to the controller.
-
公开(公告)号：US20190096494A1
公开(公告)日：2019-03-28
申请号：US15717554
申请日：2017-09-27
Applicant: Micron Technology, Inc.
Inventor： Aliasgar S. Madraswala , Kristopher H. Gaewsky , Naveen Vittal Prabhu , Purval S. Sule , Trupti Bemalkhedkar , Nehul N. Tailor , Quan H. Ngo , Dheeraj Srinivasan
CPC classification number: G11C16/3459 , G11C11/5628 , G11C16/0458 , G11C16/10 , G11C16/34 , G11C2211/5621 , G11C2211/5644 , G11C2211/5648
Abstract: Various embodiments, disclosed herein, can include apparatus and methods to perform a one check failure byte (CFBYTE) scheme in programming of a memory device. In programming memory cells in which each memory cell can store multiple bits, the multiple bits being a n-tuple of bits of a set of n-tuples of bits with each n-tuple of the set associated with a level of a set of levels of threshold voltages for the memory cells. Verification of a program algorithm can be structured based on a programming algorithm that proceeds in a progressive manner by placing a threshold voltage of one level/distribution at a time. The routine of this progression can be used to perform just one failure byte check for that specific target distribution only, thus eliminating the need to check failure byte for all subsequent target distribution during every stage of program algorithm. Additional apparatus, systems, and methods are disclosed.
-
Patent Agency Ranking
公开(公告)号：US20180301193A1
公开(公告)日：2018-10-18
申请号：US15531283
申请日：2017-03-21
Applicant: Micron Technology, Inc.
Inventor： Dheeraj Srinivasan , Jeffrey M. Tsai , Ali Mohammadzadeh , Terry M. Grunzke
Abstract: The present disclosure relates to apparatuses and methods for an automated dynamic word line start voltage (ADWLSV). An example apparatus includes a controller and a memory device. The memory device is configured to maintain, internal to the memory device, a status of a number of open blocks in the memory device. The status can include a programming operation being initiated in the respective number of open blocks. Responsive to receipt of, from the controller, a request to direct initiation of the programming operation to a word line, determine a group of memory cells associated with the word line that programs first relative to other groups of memory cells associated with the word line and maintain, included in the status of an open block, a voltage at which the group of memory cells is the first group to program.
-
公开(公告)号：US12094547B2
公开(公告)日：2024-09-17
申请号：US17893364
申请日：2022-08-23
Applicant: Micron Technology, Inc.
Inventor： Violante Moschiano , Ali Mohammadzadeh , Walter Di Francesco , Dheeraj Srinivasan
CPC classification number: G11C16/3459 , G11C7/1039 , G11C16/102 , G11C16/26
Abstract: Described are systems and methods for implementing continuous memory programming operations. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of conductive lines; and a controller coupled to the memory array. The controller performs operations comprising: performing a memory programming operation with respect to a set of memory cells of the memory array, wherein the memory programming operation comprises a sequence of programming pulses applied to one or more conductive lines electrically coupled to the set of memory cells; responsive to receiving a command to perform a memory access operation, suspending the memory programming operation after performing a current programming pulse of the sequence of programming pulses, wherein the current programming pulse is performed at a first voltage level; initiating the memory access operation; and resuming the memory programming operation by performing a next programming pulse at a second voltage level that exceeds the first voltage level.
-
公开(公告)号：US11972135B2
公开(公告)日：2024-04-30
申请号：US17590650
申请日：2022-02-01
Applicant: Micron Technology, Inc.
Inventor： Eric N. Lee , Dheeraj Srinivasan
IPC: G06F3/06
CPC classification number: G06F3/0653 , G06F3/0604 , G06F3/0673
Abstract: A memory system includes multiple dice having multiple planes. A processing device is coupled to the dice and performs controller operations including receiving a status indicator signal comprising a pulse that is asserted by one or more planes of the multiple dice. In response to receiving the pulse, the processing device performs at least one of: a first status check of dice operations being performed by the multiple dice at an expiration of a polling delay period; or a second status check of the dice operations in response to detecting the pulse being deasserted. The processing device terminates performances of status checks while the status indicator signal remains deasserted.
-
公开(公告)号：US20230352098A1
公开(公告)日：2023-11-02
申请号：US18132489
申请日：2023-04-10
Applicant: Micron Technology, Inc.
Inventor： Nagendra Prasad Ganesh Rao , Dheeraj Srinivasan , Paing Z. Htet , Sead Zildzic, JR. , Violante Moschiano
CPC classification number: G11C16/26 , G11C16/0483 , G11C16/30
Abstract: A memory device includes a memory array and control logic, operatively coupled to the memory array, to perform operations including causing a read operation to be initiated with respect to a set of target cells, obtaining cell state information for each respective group of adjacent cells, for each target cell of the set of target cells, determining a state information bin of a set of state information bins based on the cell state information for its respective group of adjacent cells, and assigning each target cell of the set of target cells to the respective state information bin. Each state information bin of the set of state information bins defines a respective boost voltage level offset to be applied to perform boost voltage modulation.
-
公开(公告)号：US20230060312A1
公开(公告)日：2023-03-02
申请号：US17893364
申请日：2022-08-23
Applicant: Micron Technology, Inc.
Inventor： Violante Moschiano , Ali Mohammadzadeh , Walter Di Francesco , Dheeraj Srinivasan
Abstract: Described are systems and methods for implementing continuous memory programming operations. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of conductive lines; and a controller coupled to the memory array. The controller performs operations comprising: performing a memory programming operation with respect to a set of memory cells of the memory array, wherein the memory programming operation comprises a sequence of programming pulses applied to one or more conductive lines electrically coupled to the set of memory cells; responsive to receiving a command to perform a memory access operation, suspending the memory programming operation after performing a current programming pulse of the sequence of programming pulses, wherein the current programming pulse is performed at a first voltage level; initiating the memory access operation; and resuming the memory programming operation by performing a next programming pulse at a second voltage level that exceeds the first voltage level.
-
-
-
-
-
-
-
-
-
Search Results
63
records
(took 0.016 seconds)
