公开(公告)号：US20220068426A1

公开(公告)日：2022-03-03

申请号：US17001723

申请日：2020-08-25

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Niccolo' Righetti ,  Jeffrey S. McNeil, JR. ,  Akira Goda ,  Todd A. Marquart ,  Mark A. Helm ,  Gil Golov ,  Jeremy Binfet ,  Carmine Miccoli ,  Giuseppina Puzzilli

IPC: G11C29/44 ,  G11C29/42 ,  G11C29/12 ,  G06F11/07 ,  G06F11/30

Abstract: A system includes a memory device having a plurality of groups of memory cells and a processing device communicatively coupled to the memory device. The processing device is be configured to read a first group of memory cells of the plurality to determine a calibrated read voltage associated with the group of memory cells. The processing device is further configured to determine, using the calibrated read voltage associated with the first group of memory cells, a bit error rate (BER) of a second group of memory cells of the plurality. Prior to causing the memory device to perform a copyback operation on the plurality of groups of memory cells, the processing device is further configured to determine whether to perform a subsequent read voltage calibration on at least the second group of the plurality based, at least partially, on a comparison between the determined BER and a threshold BER.

公开(公告)号：US20220066642A1

公开(公告)日：2022-03-03

申请号：US17006978

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Niccolo' Righetti ,  Jeffrey S. McNeil Jr. ,  Akira Goda ,  Todd A. Marquart ,  Mark A. Helm ,  Gil Golov ,  Jeremy Binfet ,  Carmine Miccoli ,  Giuseppina Puzzilli

IPC: G06F3/06

Abstract: A method includes performing a copyback operation comprising transferring, using an internal processing device, user data and header data corresponding to the user data from a first block of memory in a memory device to a register in the memory device, decoupling the user data from the header data, performing an error correction code (ECC) operation on updated header data using an external processing device, transferring, via the external processing device, the updated header data to the register, and transferring the user data and the updated header data from the register to a second block of memory in the memory device.

公开(公告)号：US20150311115A1

公开(公告)日：2015-10-29

申请号：US14265168

申请日：2014-04-29

Applicant: Micron Technology, Inc.

Inventor： Niccolo' Righetti ,  Sara Vigano ,  Emilio Camerlenghi

IPC: H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/76877 ,  H01L27/0688 ,  H01L27/105

Abstract: Some embodiments include methods of forming memory arrays. An assembly is formed which has an upper level over a lower level. The lower level includes circuitry. The upper level includes semiconductor material within a memory array region, and includes insulative material in a region peripheral to the memory array region. First and second trenches are formed to extend into the semiconductor material. The first and second trenches pattern the semiconductor material into a plurality of pedestals. The second trenches extend into the peripheral region. Contact openings are formed within the peripheral region to extend from the second trenches to the first level of circuitry. Conductive material is formed within the second trenches and within the contact openings. The conductive material forms sense/access lines within the second trenches and forms electrical contacts within the contact openings to electrically couple the sense/access lines to the lower level of circuitry.

Abstract translation: 一些实施例包括形成存储器阵列的方法。 形成了在较低水平上具有较高水平的组件。 下层包括电路。 上层包括存储器阵列区域内的半导体材料，并且在存储器阵列区域周围的区域中包括绝缘材料。 第一和第二沟槽形成为延伸到半导体材料中。 第一和第二沟槽将半导体材料图案化成多个基座。 第二沟槽延伸到周边区域。 在周边区域内形成接触开口以从第二沟槽延伸到电路的第一级。 导电材料形成在第二沟槽内部和接触开口内。 导电材料在第二沟槽内形成感测/接入线，并在接触开口内形成电接触，以将感测/接入线电耦合到较低级别的电路。

公开(公告)号：US12260916B2

公开(公告)日：2025-03-25

申请号：US18404827

申请日：2024-01-04

Applicant: Micron Technology, Inc.

Inventor： Zhongguang Xu ,  Nicola Ciocchini ,  Zhenlei Shen ,  Charles See Yeung Kwong ,  Murong Lang ,  Ugo Russo ,  Niccolo' Righetti

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/26 ,  G11C16/34

Abstract: A processing device in a memory sub-system initiates a partial block handling protocol for a closed block of a memory device, the block comprising a plurality of wordlines. The processing device further sends a first programming command to the memory device to program one or more wordlines of the block with first padding data having a first data pattern, wherein the one or more wordlines are adjacent to a last wordline of the block programmed before the block was closed. In addition, the processing device sends a second programming command to the memory device to program all of a set of remaining wordlines of the block with second padding data having a second data pattern comprising fewer bits of data per cell than the first data pattern.

公开(公告)号：US12131788B2

公开(公告)日：2024-10-29

申请号：US17895886

申请日：2022-08-25

Applicant: Micron Technology, Inc.

Inventor： Nicola Ciocchini ,  Animesh R. Chowdhury ,  Kishore Kumar Muchherla ,  Akira Goda ,  Jung Sheng Hoei ,  Niccolo' Righetti ,  Jonathan S. Parry

IPC: G11C7/00 ,  G11C16/08 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C16/3427 ,  G11C16/08 ,  G11C16/26

Abstract: Methods, systems, and apparatuses include receiving a read command including a logical address. The read command is directed to a portion of memory composed of blocks and each block is composed of wordline groups. The physical address for the read command is identified using the logical address. The wordline group is determined using the physical address. A slope factor is retrieved using the wordline group. A read counter is incremented using the slope factor.

公开(公告)号：US20240256142A1

公开(公告)日：2024-08-01

申请号：US18420491

申请日：2024-01-23

Applicant: Micron Technology, Inc.

Inventor： Chun Sum Yeung ,  Pitamber Shukla ,  Zhongyuan Lu ,  Niccolo' Righetti

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/064 ,  G06F3/0679

Abstract: Methods, systems, and devices for managing partially programmed blocks are described. Based on writing data stored in a first block to a second block, a determination of whether to program the first block into a fully programmed state may be made based on whether the first block is storing the data in the partially programmed state. Based on determining whether to program the first block, the first block may be maintained in the fully programmed state until an erase operation is performed for the first block.

公开(公告)号：US20240020020A1

公开(公告)日：2024-01-18

申请号：US17867204

申请日：2022-07-18

Applicant: Micron Technology, Inc.

Inventor： Sandeep Reddy Kadasani ,  Pitamber Shukla ,  Scott Anthony Stoller ,  Niccolo' Righetti

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0688 ,  G06F3/0653 ,  G06F3/064

Abstract: A set of threshold voltage distribution width measurements are obtained for a block in a memory device. An endurance estimate is determined for the block based on the threshold voltage distribution width measurements. The endurance estimate comprises an indication of an estimated number of program/erase cycles during which data can be reliably stored by the block. One or more parameters of the block are managed based on the endurance estimate.

公开(公告)号：US11797216B2

公开(公告)日：2023-10-24

申请号：US17867489

申请日：2022-07-18

Applicant: Micron Technology, Inc.

Inventor： Vamsi Pavan Rayaprolu ,  Giuseppina Puzzilli ,  Karl D. Schuh ,  Jeffrey S. McNeil, Jr. ,  Kishore K. Muchherla ,  Ashutosh Malshe ,  Niccolo' Righetti

IPC: G06F3/06 ,  G11C11/56 ,  G11C16/34 ,  G11C29/50

CPC classification number: G06F3/0652 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0649 ,  G06F3/0653 ,  G06F3/0679 ,  G11C11/5642 ,  G11C16/349 ,  G11C29/50004

Abstract: A signal associated with performance of a memory operation can be applied to a memory cell of a first group of memory cells that have undergone PECs within a first range. The signal can have a first magnitude corresponding to a second range of PECs. Whether differences between a first target voltage and the signal and between a second target voltage and the applied signal are at least the threshold value can be determined. Responsive to determining that the differences are at least the threshold value, the first group of memory cells can be associated with a first calibration cluster and the signal having a second magnitude corresponding to a third range of PECs can be applied to a memory cell of a second group of memory cells that have undergone respective quantities of PECs within the second range.

公开(公告)号：US11762779B1

公开(公告)日：2023-09-19

申请号：US17860293

申请日：2022-07-08

Applicant: Micron Technology, Inc.

Inventor： Zhongyuan Lu ,  Niccolo' Righetti

IPC: G06F12/0895

CPC classification number: G06F12/0895 ,  G06F2212/254

Abstract: Various embodiments enable read buffering in connection with data block transfer on a memory device. For some embodiments, read buffering from a set of cache blocks is enabled during a period of wait time after data is copied (e.g., data is transferred, such as part of a compaction operation) from the set of cache blocks to a set of non-cache blocks. In various embodiments, after the wait time, data stored on the set of cache blocks is erased (e.g., the set of cache blocks is released) and read buffering from the set of cache blocks is disabled.

公开(公告)号：US20230289062A1

公开(公告)日：2023-09-14

申请号：US18121494

申请日：2023-03-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jeffrey S. McNeil ,  Jonathan S. Parry ,  Ugo Russo ,  Akira Goda ,  Kishore Kumar Muchherla ,  Violante Moschiano ,  Niccolo' Righetti ,  Silvia Beltrami

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0679

Abstract: Control logic in a memory device causes a first pulse to be applied to a plurality of word lines coupled to respective memory cells in a memory array during an erase operation. The control logic further causes a second pulse to be applied to a first set of word lines of the plurality of word lines to bias the first set of word lines to a first voltage. The control logic can cause a third pulse to be applied to a second set of word lines of the plurality of word lines to bias the second set of word lines to a second voltage and cause a fourth pulse to be applied to a source line of the memory array to erase the respective memory cells coupled to the first set of word lines and to program the respective memory cells coupled to the second set of word lines.