公开(公告)号：US11812610B2

公开(公告)日：2023-11-07

申请号：US16539700

申请日：2019-08-13

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Rita J. Klein ,  Jordan D. Greenlee

IPC: H10B43/35 ,  H10B43/27 ,  H10B41/27 ,  H10B41/35

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: Electronic devices (e.g., semiconductor devices, which may be configured for 3D NAND memory devices), comprise pillars extending through a stack of alternating conductive tiers and insulative tiers. The conductive tiers, which may include control gates for access lines (e.g., word lines), include conductive rails along an outer sidewall of the conductive tiers, distal from the pillars extending through the conductive tiers. The conductive rails protrude laterally beyond outer sidewalls of the insulative tiers. The conductive rails increase the amount of conductive material that may otherwise be in the conductive tiers, which may enable the conductive material to exhibit a lower electrical resistance, improving operational performance of the electronic devices.

公开(公告)号：US20230290721A1

公开(公告)日：2023-09-14

申请号：US17689527

申请日：2022-03-08

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Jiewei Chen ,  Sijia Yu ,  Chieh Hsien Quek ,  Rita J. Klein ,  Nancy M. Lomeli

IPC: H01L23/522 ,  H01L23/532 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L23/5226 ,  H01L23/53257 ,  H01L23/53271 ,  H01L23/5329 ,  H01L27/11556 ,  H01L27/11582

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Individual of the conductive tiers comprise laterally-outer edges comprising conductive molybdenum-containing metal material extending horizontally-along its memory block. Channel-material strings extend through the insulative tiers and the conductive tiers. At least one of conductive or semiconductive material is formed extending horizontally-along the memory blocks laterally-outward of the laterally-outer edges comprising the conductive molybdenum-containing metal material that extends horizontally-along its memory block. Insulator material extending horizontally-along the memory blocks is formed laterally-outward of the at least one of the conductive or the semiconductive material that is laterally-outward of the laterally-outer edges comprising the conductive molybdenum-containing metal material. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US11705500B2

公开(公告)日：2023-07-18

申请号：US17180312

申请日：2021-02-19

Applicant: Micron Technology, Inc.

Inventor： David Ross Economy ,  Rita J. Klein ,  Jordan D. Greenlee ,  John Mark Meldrim ,  Brenda D. Kraus ,  Everett A. McTeer

IPC: H01L29/49 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11565 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H01L29/4966 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B41/35 ,  H10B43/35

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and control gate levels. Channel material extends vertically along the stack. The control gate levels comprising conductive regions. The conductive regions include at least three different materials. Charge-storage regions are adjacent the control gate levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.

公开(公告)号：US20230154856A1

公开(公告)日：2023-05-18

申请号：US18157962

申请日：2023-01-23

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John D. Hopkins ,  Everett A. McTeer ,  Yiping Wang ,  Rajesh Balachandran ,  Rita J. Klein ,  Yongjun J. Hu

IPC: H01L23/538 ,  H01L23/532 ,  H01L21/768 ,  G11C5/06 ,  G11C5/02 ,  H01L27/06

CPC classification number: H01L23/5386 ,  H01L23/5385 ,  H01L23/5384 ,  H01L23/53204 ,  H01L21/76877 ,  G11C5/06 ,  G11C5/025 ,  H01L21/76802 ,  H01L27/0688

Abstract: A microelectronic device comprises a stack structure comprising insulative levels vertically interleaved with conductive levels. The conductive levels individually comprise a first conductive structure, and a second conductive structure laterally neighboring the first conductive structure, the second conductive structure exhibiting a concentration of 3-phase tungsten varying with a vertical distance from a vertically neighboring insulative level. The microelectronic device further comprises slot structures vertically extending through the stack structure and dividing the stack structure into block structures, and strings of memory cells vertically extending through the stack structure, the first conductive structures between laterally neighboring strings of memory cells, the second conductive structures between the slot structures and strings of memory cells nearest the slot structures. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US11600630B2

公开(公告)日：2023-03-07

申请号：US16988156

申请日：2020-08-07

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Nancy M. Lomeli ,  John D. Hopkins ,  Jiewei Chen ,  Indra V. Chary ,  Jun Fang ,  Vladimir Samara ,  Kaiming Luo ,  Rita J. Klein ,  Xiao Li ,  Vinayak Shamanna

IPC: H01L27/11568 ,  H01L27/11556 ,  H01L27/11582 ,  G11C5/06 ,  H01L21/306 ,  G11C16/04 ,  G11C5/02

Abstract: Some embodiments include an integrated assembly having a source structure, and having a stack of alternating conductive levels and insulative levels over the source structure. Cell-material-pillars pass through the stack. The cell-material-pillars are arranged within a configuration which includes a first memory-block-region and a second memory-block-region. The cell-material-pillars include channel material which is electrically coupled with the source structure. Memory cells are along the conductive levels and include regions of the cell-material-pillars. A panel is between the first and second memory-block-regions. The panel has a first material configured as a container shape. The container shape defines opposing sides and a bottom of a cavity. The panel has a second material within the cavity. The second material is compositionally different from the first material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20220310522A1

公开(公告)日：2022-09-29

申请号：US17209993

申请日：2021-03-23

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John D. Hopkins ,  Everett A. McTeer ,  Yiping Wang ,  Rajesh Balachandran ,  Rita J. Klein ,  Yongjun J. Hu

IPC: H01L23/538 ,  H01L23/532 ,  H01L27/06 ,  G11C5/06 ,  G11C5/02 ,  H01L21/768

Abstract: A microelectronic device comprises a stack structure comprising insulative levels vertically interleaved with conductive levels. The conductive levels individually comprise a first conductive structure, and a second conductive structure laterally neighboring the first conductive structure, the second conductive structure exhibiting a concentration of β-phase tungsten varying with a vertical distance from a vertically neighboring insulative level. The microelectronic device further comprises slot structures vertically extending through the stack structure and dividing the stack structure into block structures, and strings of memory cells vertically extending through the stack structure, the first conductive structures between laterally neighboring strings of memory cells, the second conductive structures between the slot structures and strings of memory cells nearest the slot structures. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US20220302032A1

公开(公告)日：2022-09-22

申请号：US17806438

申请日：2022-06-10

Applicant: Micron Technology Inc.

Inventor： Jordan D. Greenlee ,  Christian George Emor ,  Luca Fumagalli ,  John D. Hopkins ,  Rita J. Klein ,  Christopher W. Petz ,  Everett A. McTeer

IPC: H01L23/535 ,  H01L23/532 ,  H01L21/768 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: A microelectronic device includes a first conductive structure, a barrier structure, a conductive liner structure, and a second conductive structure. The first conductive structure is within a first filled opening in a first dielectric structure. The barrier structure is within the first filled opening in the first dielectric structure and vertically overlies the first conductive structure. The conductive liner structure is on the barrier structure and is within a second filled opening in a second dielectric structure vertically overlying the first dielectric structure. The second conductive structure vertically overlies and is horizontally surrounded by the conductive liner structure within the second filled opening in the second dielectric structure. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

公开(公告)号：US11342265B2

公开(公告)日：2022-05-24

申请号：US16702222

申请日：2019-12-03

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Lifang Xu ,  Rita J. Klein ,  Xiao Li ,  Everett A. McTeer

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/00 ,  H01L21/768 ,  H01L27/11529 ,  H01L27/11556

Abstract: An apparatus comprising at least one contact structure. The at least one contact structure comprises a contact, an insulating material overlying the contact, and at least one contact via in the insulating material. The at least one contact structure also comprises a dielectric liner material adjacent the insulating material within the contact via, a conductive material adjacent the dielectric liner material, and a stress compensation material adjacent the conductive material and in a central portion of the at least one contact via. The stress compensation material is at least partially surrounded by the conductive material. Memory devices, electronic systems, and methods of forming the apparatus are also disclosed.

公开(公告)号：US20210375894A1

公开(公告)日：2021-12-02

申请号：US17395751

申请日：2021-08-06

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Indra V. Chary ,  Justin B. Dorhout ,  Rita J. Klein

IPC: H01L27/11529 ,  G11C5/06 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11556

Abstract: Some embodiments include an integrated assembly having a conductive expanse over conductive nodes. The conductive nodes include a first composition. A bottom surface of the conductive expanse includes a second composition which is different composition than the first composition. A stack is over the conductive expanse. The stack includes alternating first and second levels. Pillar structures extend vertically through the stack. Each of the pillar structures includes a post of conductive material laterally surrounded by an insulative liner. At least one of the posts extends through the conductive expanse to directly contact one of the conductive nodes. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11158718B2

公开(公告)日：2021-10-26

申请号：US16383862

申请日：2019-04-15

Applicant: Micron Technology, inc.

Inventor： Jordan D. Greenlee ,  Rita J. Klein ,  Everett A. McTeer ,  John Mark Meldrim

IPC: H01L29/49 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11519

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. Channel material extends vertically along the stack. The wordline levels include conductive regions which have a first metal-containing material and a second metal-containing material. The first metal-containing material at least partially surrounds the second metal-containing material. The first metal-containing material has a different crystallinity than the second metal-containing material. In some embodiments the first metal-containing material is substantially amorphous, and the second metal-containing material has a mean grain size within a range of from greater than or equal to about 5 nm to less than or equal to about 200 nm. Charge-storage regions are adjacent the wordline levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.