公开(公告)号：US10249365B2

公开(公告)日：2019-04-02

申请号：US15831718

申请日：2017-12-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vishal Sarin ,  Allahyar Vahidimowlavi

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34

Abstract: Memory devices include control logic configured to set a first start program voltage and a first stop program voltage, to load actual first data for cells to be programmed to a level greater than or equal to a first level, and to load inhibit data for cells to be programmed to a level less than a second level. After programming the cells to be programmed to the level greater than or equal to the first level, the control logic is further configured to set a second start program voltage and a second stop program voltage, to load inhibit data for the cells programmed to the level greater than or equal to the first level, and to load actual second data for the cells to be programmed to the level less than the second level, wherein the first level is one level higher than the second level.

公开(公告)号：US20180108415A1

公开(公告)日：2018-04-19

申请号：US15841490

申请日：2017-12-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca De Santis ,  Tommaso Vali ,  Kenneth J. Eldredge ,  Vishal Sarin

IPC: G11C15/04 ,  G11C16/04 ,  G11C16/10

CPC classification number: G11C15/046 ,  G11C16/0483 ,  G11C16/10 ,  G11C29/52

Abstract: Methods include receiving a pattern to be searched in a memory having a plurality of sets of memory elements with each set coupled to a separate data line and corresponding to a same set of bit positions of the pattern. Methods further include receiving a pattern of data to be programmed into a memory, programming a first data state into one memory cell of each cell pair of a plurality of cell pairs of a memory array, and programing a second data state into another memory cell of each cell pair of the plurality of cell pairs for each bit position of the pattern. Memory configured to facilitate such methods include a plurality of cell pairs, each cell pair of the plurality of cell pairs programmed to store a same bit of data corresponding to a particular bit position of a pattern to be searched in the memory.

公开(公告)号：US09471425B2

公开(公告)日：2016-10-18

申请号：US14308040

申请日：2014-06-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： William H. Radke ,  Vishal Sarin ,  Jung-Sheng Hoei

IPC: G06F12/02 ,  G06F11/10 ,  G11C11/56 ,  G11C29/52

CPC classification number: G06F11/1072 ,  G06F12/0246 ,  G06F2212/7205 ,  G06F2212/7208 ,  G11C11/5628 ,  G11C29/52 ,  G11C2211/5641

Abstract: Methods for managing data stored in a memory device facilitate managing utilization of memory of different densities. The methods include reading first data from a first number of pages or blocks of memory cells having a first density, performing a data handling operation on the read first data to generate second data, and writing the second data to a second number of pages or blocks of memory cells having a second density, wherein the second density is different than the first density, and wherein the second number is different than the first number.

Abstract translation: 用于管理存储在存储设备中的数据的方法便于管理不同密度的存储器的利用。 所述方法包括从具有第一密度的第一页数或块的存储单元读取第一数据，对读取的第一数据执行数据处理操作以产生第二数据，以及将第二数据写入第二数量的页或块 的具有第二密度的存储单元，其中所述第二密度不同于所述第一密度，并且其中所述第二数量不同于所述第一密度。

公开(公告)号：US09349474B2

公开(公告)日：2016-05-24

申请号：US13924310

申请日：2013-06-21

Applicant: Micron Technology, Inc.

Inventor： Vishal Sarin

IPC: G11C16/30 ,  G11C7/14 ,  G11C16/26 ,  G11C16/34 ,  G11C16/04

CPC classification number: G11C16/30 ,  G11C7/14 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3459

Abstract: Apparatuses, current control circuits, and methods for limiting string current in a memory are described. An example apparatus includes a memory cell string including a memory cell. The example apparatus further includes a sense circuit configured to sense a current through the memory cell string, and a select gate configured to couple the memory cell string to a source based on a select gate voltage. The example apparatus further includes a current control circuit coupled to the select gate. The current control circuit is configured to limit current through the memory cell string during a memory access operation based on a reference current.

Abstract translation: 描述了用于限制存储器中的串电流的装置，电流控制电路和方法。 示例性装置包括包括存储单元的存储单元串。 该示例设备还包括：感测电路，被配置为感测通过存储单元串的电流;以及选择栅极，被配置为基于选择栅极电压将存储单元串耦合到源极。 该示例设备还包括耦合到选择门的电流控制电路。 电流控制电路被配置为基于参考电流在存储器访问操作期间限制通过存储器单元串的电流。

公开(公告)号：US09196370B2

公开(公告)日：2015-11-24

申请号：US13943254

申请日：2013-07-16

Applicant: Micron Technology, Inc.

Inventor： Vishal Sarin ,  Frankie F. Roohparvar ,  Jung Sheng Hoei

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/26 ,  G11C11/56 ,  G11C16/34

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/3418

Abstract: The present disclosure includes methods, devices, modules, and systems for reducing noise in semiconductor devices. One method embodiment includes applying a reset voltage to a control gate of a semiconductor device for a period of time. The method further includes sensing the state of the semiconductor device after applying the reset voltage.

Abstract translation: 本公开包括用于降低半导体器件中的噪声的方法，装置，模块和系统。 一个方法实施例包括将复位电压施加到半导体器件的控制栅极一段时间。 该方法还包括在施加复位电压之后感测半导体器件的状态。

公开(公告)号：US09147476B2

公开(公告)日：2015-09-29

申请号：US14108822

申请日：2013-12-17

Applicant: Micron Technology, Inc.

Inventor： Vishal Sarin ,  William H. Radke ,  Frankie F. Roohparvar

IPC: G11C11/00 ,  G11C16/10 ,  G11C16/04 ,  G11C16/34

Abstract: Methods of programming a memory and memories are disclosed. In at least one embodiment, a memory is programmed by determining a pretarget threshold voltage for a selected cell, wherein the pretarget threshold voltage is determined using pretarget threshold voltage values for at least one neighbor cell of the selected cell.

公开(公告)号：US08705299B2

公开(公告)日：2014-04-22

申请号：US13894543

申请日：2013-05-15

Applicant: Micron Technology, Inc.

Inventor： Vishal Sarin ,  Dzung H. Nguyen ,  William H. Radke

IPC: G11C7/00

CPC classification number: G11C29/04 ,  G11C29/808 ,  G11C29/82 ,  G11C29/848

Abstract: An apparatus has a controller. The controller is configured to address a non-defective memory block of a sequence of memory blocks in place of a defective memory block of the sequence of memory blocks such that the non-defective memory block replaces the defective memory block. The non-defective memory block is a proximate non-defective memory block following the defective memory block in the sequence of memory blocks that is available to replace the defective memory block. The controller is configured to apply a voltage-delay correction to the non-defective memory block that replaces the defective memory block based on the actual location of the non-defective memory block.

Abstract translation: 装置具有控制器。 控制器被配置为代替存储器块序列的缺陷存储器块来寻址一系列存储器块的无缺陷存储器块，使得非缺陷存储器块替换有缺陷的存储器块。 无缺陷存储器块是跟随可用于替换有缺陷的存储器块的存储器块序列中的缺陷存储器块之后的邻近的无缺陷存储器块。 所述控制器被配置为基于所述无缺陷存储器块的实际位置对所述缺陷存储器块进行替换的所述非缺陷存储器块施加电压延迟校正。

公开(公告)号：US20140098607A1

公开(公告)日：2014-04-10

申请号：US14046640

申请日：2013-10-04

Applicant: Micron Technology, Inc.

Inventor： Vishal Sarin ,  Jung Sheng Hoei ,  Frankie Roohparvar ,  Giulio-Giuseppe Marotta

IPC: G11C16/12

CPC classification number: G11C16/12 ,  G11C7/16 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/28 ,  G11C2211/5621 ,  G11C2211/5634 ,  G11C2211/5642

Abstract: The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying a ramping voltage to a control gate of a memory cell and to an analog-to-digital converter (ADC). The aforementioned embodiment of a method also includes detecting an output of the ADC at least partially in response to when the ramping voltage causes the memory cell to trip sense circuitry.

Abstract translation: 本公开包括用于操作存储器单元的方法，设备，模块和系统。 一种方法实施例包括将斜波电压施加到存储器单元的控制栅极和模数转换器（ADC）。 上述方法的实施例还包括响应于斜坡电压何时使存储器单元跳闸感测电路至少部分地检测ADC的输出。

公开(公告)号：US20130272070A1

公开(公告)日：2013-10-17

申请号：US13919350

申请日：2013-06-17

Applicant: Micron Technology, Inc.

Inventor： Vishal Sarin ,  Jung-Sheng Hoei ,  Frankie F. Rooparvar

IPC: G11C16/26

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/28 ,  G11C16/3481 ,  G11C27/02 ,  G11C27/024 ,  G11C2211/5634

Abstract: Memory devices, methods, and sample and hold circuits are disclosed, including a memory device that includes a sample and hold circuit coupled to a bit line. One such sample and hold circuit includes a read circuit, a verify circuit, and a reference circuit. The read circuit stores a read threshold voltage that was read from a selected memory cell. The verify circuit stores a target threshold voltage that is compared to the read threshold voltage to generate an inhibit signal when the target and read threshold voltages are substantially equal. The reference circuit stores a reference threshold voltage that can be used to translate the read threshold voltage to compensate for a transistor voltage drop and/or temperature variations.

公开(公告)号：US20130166815A1

公开(公告)日：2013-06-27

申请号：US13770059

申请日：2013-02-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vishal Sarin ,  Jung-Sheng Hoei ,  Jonathan Pabustan ,  Frankie F. Roohparvar

IPC: G06F12/02

CPC classification number: G11C11/5642 ,  G11C7/16 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C27/005 ,  G11C2211/5621 ,  G11C2211/5622 ,  G11C2211/5642 ,  G11C2216/14

Abstract: A memory controller has a digital signal processor. The digital signal processor is configured to output a digital data signal of M+N bits of program data intended for programming a memory cell of a memory device. The digital signal processor is configured to receive a digital data signal of M+L bits read from the memory cell of the memory device and to retrieve from the received digital data signal M bits of data that were stored in the memory cell.

Abstract translation: 存储器控制器具有数字信号处理器。 数字信号处理器被配置为输出用于对存储器件的存储器单元进行编程的程序数据的M + N位的数字数据信号。 数字信号处理器被配置为接收从存储器件的存储器单元读取的M + L位的数字数据信号，并从接收的数字数据信号M中取回存储在存储单元中的数据位。