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    Multi-chip package, controlling method of multi-chip package and security chip
    41.
    发明授权
    Multi-chip package, controlling method of multi-chip package and security chip 有权

    公开(公告)号：US10969991B2

    公开(公告)日：2021-04-06

    申请号：US15998456

    申请日：2018-08-15

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Chia-Jung Chen ,  Chin-Hung Chang ,  Ken-Hui Chen

    IPC: G06F3/06

    Abstract: A multi-chip package, a controlling method of the multi-chip package and a security chip are provided. The multi-chip package includes a memory chip and a security chip. The security chip is coupled between the memory chip and a host. The security chip includes a processing circuit. The processing circuit is for enabling a security path to input an input-output signal into the processing circuit for executing a security procedure and accessing the memory chip, if a command is received by the processing circuit and the command includes a security requirement.

    MEMORY CIRCUIT
    43.
    发明申请
    MEMORY CIRCUIT 审中-公开

    公开(公告)号：US20200185010A1

    公开(公告)日：2020-06-11

    申请号：US16534992

    申请日：2019-08-07

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Su-Chueh Lo ,  Ken-Hui Chen ,  Kuen-Long Chang ,  Ming-Chih Hsieh

    IPC: G11C5/14 ,  G11C7/10 ,  G11C7/06

    Abstract: A data receiving stage circuit of a memory circuit receives a serial input signal and a chip enable signal. A data writing circuit of the memory circuit generates at least one of a command signal and a data signal according to the serial input signal. A power supply circuit of the memory circuit generates an operating voltage for a memory cell array to perform a data access operation. A data output stage circuit of the memory circuit outputs a readout data. A controller of the memory circuit performs a switching operation of an operating state of the memory circuit according to a change of the chip enable signal. The controller determines a disable or enable state of the data receiving stage circuit, the data writing circuit, the power supply circuit, and the data output stage circuit according to the operating state.

    NESTED WRAP-AROUND MEMORY ACCESS
    46.
    发明申请
    NESTED WRAP-AROUND MEMORY ACCESS 审中-公开

    公开(公告)号：US20190073300A1

    公开(公告)日：2019-03-07

    申请号：US16180930

    申请日：2018-11-05

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Kuen-Long Chang ,  Ken-Hui Chen ,  Chin-Hung Chang

    IPC: G06F12/06

    Abstract: A nested wrap-around technology includes an address counter and associated logic for generating addresses to perform a nested wrap-around access operation. The nested wrap-around access operation may be a read or a write operation. A wrap-around section length and a wrap-around count define a wrap-around block. A wrap starting address, initially set to a supplied start address, is offset from a lower boundary of a wrap-around section. Access starts at a wrap starting address and proceeds in a wrap-around manner within a wrap-around section. After access of the address immediately preceding the wrap starting address, the wrap starting address is incremented by the wrap-around section length, or, if the wrap-around section is the last one in the wrap-around block, the wrap starting address is set to the lower boundary of the wrap-around block plus the offset. Access continues until a termination event.

    NON-VOLATILE MEMORY WITH SECURITY KEY STORAGE
    48.
    发明申请
    NON-VOLATILE MEMORY WITH SECURITY KEY STORAGE 审中-公开

    公开(公告)号：US20180039581A1

    公开(公告)日：2018-02-08

    申请号：US15601582

    申请日：2017-05-22

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Shih-Chang Huang

    IPC: G06F12/14 ,  H04L9/08 ,  G06F13/42

    Abstract: A system and method for utilizing a security key stored in non-volatile memory, and for generating a PUF-based data set on an integrated circuit including non-volatile memory cells, such as flash memory cells, are described. The method includes storing a security key in a particular block in a plurality of blocks of the non-volatile memory array; utilizing, in a security logic circuit coupled to the non-volatile memory array, the security key stored in the particular block in a protocol to enable access via a port by external devices or communication networks to data stored in blocks in the plurality of blocks; and enabling read-only access to the particular block by the security logic for use in the protocol, and preventing access to the particular block via the port.

    I/O BUS SHARED MEMORY SYSTEM
    50.
    发明申请
    I/O BUS SHARED MEMORY SYSTEM 审中-公开

    公开(公告)号：US20170109297A1

    公开(公告)日：2017-04-20

    申请号：US15215439

    申请日：2016-07-20

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Kuen-Long Chang ,  Ken-Hui Chen ,  Chin-Hung Chang

    IPC: G06F13/16 ,  G06F13/42

    CPC classification number: G06F13/1663 ,  G06F13/4282

    Abstract: A memory system has a plurality of memory devices coupled with a hub in discrete and shared port arrangements. A plurality of bus lines connect the plurality of memory devices to the hub, including a first subset of bus lines connected in a point-to-point configuration between the hub and a particular memory device, and a second subset of bus lines connected to all the memory devices in the plurality of memory devices including the particular memory device. Bus operation logic is configured to use the first subset of bus lines in a first operation accessing the particular memory device while simultaneously using the second subset of bus lines in a second operation accessing a different selected memory device of the plurality of memory devices.

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