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53 条记录 (耗时 0.026 秒)

    Semiconductor device and method of the semiconductor device
    43.
    发明授权
    Semiconductor device and method of the semiconductor device 失效
    半导体器件的半导体器件和方法

    公开(公告)号：US06912172B2

    公开(公告)日：2005-06-28

    申请号：US10718562

    申请日：2003-11-24

    申请人： Kazuki Honma ,  Yoshiki Kawajiri ,  Masashi Wada ,  Mikio Sugawara ,  Hirofumi Sonoyama

    发明人： Kazuki Honma ,  Yoshiki Kawajiri ,  Masashi Wada ,  Mikio Sugawara ,  Hirofumi Sonoyama

    IPC分类号： G01R31/28 ,  G11C5/14 ,  G11C16/02 ,  G11C16/16 ,  G11C16/30 ,  G11C17/00 ,  G11C29/00 ,  G11C29/02 ,  G11C29/12 ,  G11C29/44 ,  G11C8/00

    CPC分类号： G11C29/028 ,  G11C5/14 ,  G11C16/04 ,  G11C16/30 ,  G11C29/006 ,  G11C29/02 ,  G11C29/12005 ,  G11C2029/5004

    摘要： Disclosed are a semiconductor chip which is uniquely value-added, a semiconductor integrated circuit device which improves the productivity and yield of products and facilitates the production management, and a method of manufacturing of semiconductor integrated circuit devices which enables the improvement of productivity and yield of products and the rational demand-responsive production management. The semiconductor chip includes a common circuit block which is operative at a first voltage and a second voltage that is higher than the first voltage, a first circuit block which is designed to fit the first voltage and operate in unison with the common circuit block, a second circuit block which is designed to fit the second voltage and operate in unison with the common circuit block, and a voltage type setup circuit which activates one of the first and second circuit blocks, with a first identification record indicative of the operability at the first voltage or a second identification record indicative of the operability only at the second voltage being held by the chip.

    摘要翻译： 公开了一种独特增值的半导体芯片，提高产品的生产率和产量并促进生产管理的半导体集成电路器件，以及制造半导体集成电路器件的方法，其能够提高生产率和产量 产品和理性需求响应生产管理。 半导体芯片包括在第一电压和第二电压下操作的公共电路块，第二电压高于第一电压，被设计为适合第一电压并与公共电路块一致操作的第一电路块， 第二电路块，其被设计成适合第二电压并且与公共电路块一致地操作;以及电压类型建立电路，其激活第一和第二电路块中的一个，电压类型建立电路具有第一识别记录，其指示第一电压块的可操作性 电压或第二识别记录，仅指示在芯片所保持的第二电压下的可操作性。

    Semiconductor memory device
    44.
    发明授权
    Semiconductor memory device 失效

    公开(公告)号：US06618298B2

    公开(公告)日：2003-09-09

    申请号：US10144036

    申请日：2002-05-14

    申请人： Kazuki Honma ,  Masashi Wada ,  Shuichi Kuwahara

    发明人： Kazuki Honma ,  Masashi Wada ,  Shuichi Kuwahara

    IPC分类号： G11C700

    CPC分类号： G11C29/12

    摘要： The semiconductor memory device of the present invention is provided with a switching element comprised of a single channel MOS transistor at a halfway of a path used to transmit a high voltage supplied to the memory array via the external terminal at the time of a test performance, so that the switching element is turned off when a word line is changed to another, thereby resetting of the supply voltage having been required conventionally for each test performance is omitted.

    Semiconductor integrated circuit device having reference voltage generating section
    46.
    发明授权
    Semiconductor integrated circuit device having reference voltage generating section 失效
    具有参考电压产生部分的半导体集成电路器件

    公开(公告)号：US06512398B1

    公开(公告)日：2003-01-28

    申请号：US09572443

    申请日：2000-05-17

    申请人： Hirofumi Sonoyama ,  Yoshiki Kawajiri ,  Masashi Wada ,  Jun Eto ,  Shinji Kawai

    发明人： Hirofumi Sonoyama ,  Yoshiki Kawajiri ,  Masashi Wada ,  Jun Eto ,  Shinji Kawai

    IPC分类号： G01R1900

    CPC分类号： G11C5/143 ,  G01R19/16552 ,  G05F3/242 ,  G11C16/30

    摘要： The reliability of a semiconductor integrated circuit device is remarkably improved by minimizing the fluctuations of the detection level of the supply voltage due to the manufacturing process and/or other factors. In the semiconductor integrated circuit device according to the invention, a differential amplifier circuit SA amplifies the differential voltage representing the difference between the reference voltage VREF generated by a reference voltage generating section 16 and the detection voltage obtained by dividing a supply voltage VCC by means of resistors 27 and 28 and outputs it as a detection signal K. The reference voltage generating section 16 generates reference voltage VREF from the base-emitter voltage of a bipolar transistor that is minimally affected by temperature and the manufacturing process so that the fluctuations of the detection level of the supply voltage VCC can be minimized.

    摘要翻译： 通过最小化由于制造过程和/或其他因素导致的电源电压的检测水平的波动，可以显着提高半导体集成电路器件的可靠性。 在根据本发明的半导体集成电路器件中，差分放大器电路SA放大表示由参考电压产生部分16产生的参考电压VREF与由电源电压VCC分压所获得的检测电压之间的差异的差分电压， 电阻器27和28并将其输出作为检测信号K.参考电压产生部分16从由温度和制造过程影响最小的双极晶体管的基极 - 发射极电压产生参考电压VREF，使得检测的波动 电源电压VCC的电平可以最小化。

    Semiconductor memory device that can realize high speed data read out
    47.
    发明授权
    Semiconductor memory device that can realize high speed data read out 失效
    可实现高速数据读出的半导体存储器件

    公开(公告)号：US5852583A

    公开(公告)日：1998-12-22

    申请号：US848391

    申请日：1997-05-08

    申请人： Yasuhiko Taito ,  Shinji Kawai ,  Shinichi Kobayashi ,  Akinori Matsuo ,  Masashi Wada

    发明人： Yasuhiko Taito ,  Shinji Kawai ,  Shinichi Kobayashi ,  Akinori Matsuo ,  Masashi Wada

    IPC分类号： G11C17/00 ,  G11C8/08 ,  G11C16/06 ,  G11C8/00

    CPC分类号： G11C8/08

    摘要： Following latching of a word line select signal by a latch circuit, a transfer gate is turned off. When a word line is selected, the voltage applied to the latch circuit is shifted to a desired level to apply a desired voltage to the word line from a word line driver. As a result, a predecode signal is applied to a small size buffering circuit to be transmitted to the word line driver at a potential level between Vcc-GND. Therefore, the parasitic capacitance accompanying a predecode signal is reduced.

    摘要翻译： 在通过锁存电路锁存字线选择信号之后，转移门被关闭。 当选择字线时，施加到锁存电路的电压被移动到期望的电平，以从字线驱动器向字线施加期望的电压。 结果，将预解码信号施加到小尺寸缓冲电路，以在Vcc-GND之间的电位电平发送到字线驱动器。 因此，伴随预解码信号的寄生电容减少。

    Magnetic resonance imaging apparatus having vibration damping means on gradient coil
    48.
    发明授权
    Magnetic resonance imaging apparatus having vibration damping means on gradient coil 失效
    具有梯度线圈上的减震装置的磁共振成像装置

    公开(公告)号：US5345177A

    公开(公告)日：1994-09-06

    申请号：US32665

    申请日：1993-03-17

    申请人： Taichi Sato ,  Yoshiharu Mohri ,  Kihachiro Tanaka ,  Takao Honmei ,  Masayuki Otsuka ,  Masashi Wada

    发明人： Taichi Sato ,  Yoshiharu Mohri ,  Kihachiro Tanaka ,  Takao Honmei ,  Masayuki Otsuka ,  Masashi Wada

    IPC分类号： A61B5/055 ,  G01R33/20 ,  G01R33/385 ,  G01V3/00

    CPC分类号： G01R33/3854

    摘要： A magnetic resonance imaging apparatus includes a magnet for generating a static magnetic field, a gradient coil for generating a gradient magnetic field in a measurement space, and a vibration damping means which includes a container and granular material disposed in the container. The vibration damping means is installed with a supporting bolt between the gradient coil and a supporting means. Since the gradient coil is supported at a constant position without any vibration and deformation, the magnetic resonance imaging apparatus generates an accurate image signal without any acoustic noise.

    摘要翻译： 磁共振成像装置包括用于产生静磁场的磁体，用于在测量空间中产生梯度磁场的梯度线圈，以及包括容器和设置在容器中的颗粒材料的减振装置。 减震装置在梯度线圈和支撑装置之间安装有支撑螺栓。 由于梯度线圈被支撑在恒定位置而没有任何振动和变形，所以磁共振成像装置产生没有任何声学噪声的精确图像信号。

    Nonvolatile semiconductor memory device having redundant data lines and page mode programming
    49.
    发明授权
    Nonvolatile semiconductor memory device having redundant data lines and page mode programming 失效
    具有冗余数据线和页面模式编程的非易失性半导体存储器件

    公开(公告)号：US5134583A

    公开(公告)日：1992-07-28

    申请号：US440323

    申请日：1989-11-22

    申请人： Akinori Matsuo ,  Masashi Watanabe ,  Masashi Wada ,  Takeshi Wada ,  Yasuhiro Nakamura

    发明人： Akinori Matsuo ,  Masashi Watanabe ,  Masashi Wada ,  Takeshi Wada ,  Yasuhiro Nakamura

    IPC分类号： G11C16/02 ,  G11C16/06 ,  G11C17/00 ,  G11C29/00 ,  G11C29/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： G11C29/78

    摘要： A semiconductor memory device has a plurality of memory blocks, each block including a matrix arrangement of a plurality of nonvolatile memory elements. The device is also provided with at least one redundant data line which is selectively employed in place of a defective data line associated with a defective address in a memory block. The data lines corresponding to the respective memory blocks are selectively coupled to corresponding ones of first common data lines by a Y selector circuit in accordance with outputs of a first Y decoder, while a redundant data line is controllably coupled to a redundant common data line by a redundant selector circuit in accordance with an output of a redundant decoder. A plurality of data latch circuits are provided for transmitting therethrough write information data in accordance with outputs of a second Y decoder and a second redundant decoder, each one of the plurality of data latch circuits being paired with a respective one of a plurality of write amplifiers which transmit the write signals to the common data lines and redundant common data line. Therefore, of the plurality of data lines being addressed in the plurality of memory blocks, only a defective data line which corresponds to a defective address is replaced with a respective redundant data line.

    摘要翻译： 半导体存储器件具有多个存储块，每个块包括多个非易失性存储元件的矩阵排列。 该设备还设置有至少一个冗余数据线，其被选择性地用于代替与存储器块中的缺陷地址相关联的有缺陷的数据线。 对应于相应存储块的数据线根据第一Y解码器的输出由Y选择器电路选择性地耦合到相应的第一公用数据线，而冗余数据线可控地耦合到冗余公用数据线， 根据冗余解码器的输出的冗余选择器电路。 提供了多个数据锁存电路，用于根据第二Y解码器和第二冗余解码器的输出来传输写入信息数据，多个数据锁存电路中的每一个与多个写入放大器中的相应一个配对 其将写信号发送到公共数据线和冗余公用数据线。 因此，在多个存储块中寻址的多条数据线中，只有与缺陷地址对应的缺陷数据线被相应的冗余数据线替代。