公开(公告)号：US09859400B2

公开(公告)日：2018-01-02

申请号：US14677511

申请日：2015-04-02

Applicant: MaxPower Semiconductor, Inc.

Inventor： Mohamed N. Darwish ,  Jun Zeng ,  Richard A. Blanchard

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/417 ,  H01L29/739 ,  H01L29/78 ,  H01L29/40 ,  H01L29/10 ,  H01L21/265 ,  H01L21/8234 ,  H01L29/16 ,  H01L29/36 ,  H01L29/423 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/66734 ,  H01L21/26506 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/36 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/7395 ,  H01L29/7803 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7831 ,  H01L29/7835

Abstract: Methods and systems for power semiconductor devices integrating multiple trench transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.

公开(公告)号：US09847413B2

公开(公告)日：2017-12-19

申请号：US15230307

申请日：2016-08-05

Applicant: MaxPower Semiconductor Inc.

Inventor： Mohamed N. Darwish ,  Jun Zeng

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/16 ,  H03K17/687 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417

CPC classification number: H01L29/7811 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0856 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/404 ,  H01L29/407 ,  H01L29/408 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/7813 ,  H01L29/7823 ,  H01L29/7827 ,  H01L29/7835 ,  H03K17/687

Abstract: N-channel power semiconductor devices in which an insulated field plate is coupled to the drift region, and immobile electrostatic charge is also present at the interface between the drift region and the insulation around the field plate. The electrostatic charge permits OFF-state voltage drop to occur near the source region, in addition to the voltage drop which occurs near the drain region (due to the presence of the field plate).

公开(公告)号：US09842917B2

公开(公告)日：2017-12-12

申请号：US15012642

申请日：2016-02-01

Applicant: MaxPower Semiconductor, Inc.

Inventor： Mohamed N. Darwish ,  Jun Zeng ,  Richard A. Blanchard

IPC: H01L29/40 ,  H01L29/739 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/167 ,  H01L21/265 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/7393 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/402 ,  H01L29/407 ,  H01L29/408 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/7816

Abstract: Power semiconductor devices, and related methods, where majority carrier flow is divided into paralleled flows through two drift regions of opposite conductivity types.

公开(公告)号：US20170069727A1

公开(公告)日：2017-03-09

申请号：US15247510

申请日：2016-08-25

Applicant: MaxPower Semiconductor, Inc.

Inventor： Richard A. Blanchard ,  Mohamed N. Darwish ,  Jun Zeng

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/06 ,  H01L29/16 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/66068 ,  H01L21/047 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1037 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7813

Abstract: In one embodiment, a power MOSFET vertically conducts current. A bottom electrode may be connected to a positive voltage, and a top electrode may be connected to a low voltage, such as a load connected to ground. A gate and/or a field plate, such as polysilicon, is within a trench. The trench has a tapered oxide layer insulating the polysilicon from the silicon walls. The oxide is much thicker near the bottom of the trench than near the top to increase the breakdown voltage. The tapered oxide is formed by implanting nitrogen into the trench walls to form a tapered nitrogen dopant concentration. This forms a tapered silicon nitride layer after an anneal. The tapered silicon nitride variably inhibits oxide growth in a subsequent oxidation step.

Abstract translation: 在一个实施例中，功率MOSFET垂直传导电流。 底部电极可以连接到正电压，并且顶部电极可以连接到低电压，例如连接到地的负载。 诸如多晶硅的栅极和/或场板在沟槽内。 沟槽具有使多晶硅与硅壁绝缘的锥形氧化物层。 在沟槽底部附近的氧化物比靠近顶部更厚，以增加击穿电压。 通过将氮注入到沟槽壁中以形成锥形氮掺杂剂浓度来形成锥形氧化物。 这在退火之后形成锥形氮化硅层。 锥形氮化硅在随后的氧化步骤中可变地抑制氧化物生长。

公开(公告)号：US20160293743A1

公开(公告)日：2016-10-06

申请号：US15012642

申请日：2016-02-01

Applicant: MaxPower Semiconductor, Inc.

Inventor： Mohamed N. Darwish ,  Jun Zeng ,  Richard A. Blanchard

IPC: H01L29/739 ,  H01L29/167 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/7393 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/402 ,  H01L29/407 ,  H01L29/408 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/7816

Abstract: Power semiconductor devices, and related methods, where majority carrier flow is divided into paralleled flows through two drift regions of opposite conductivity types.

公开(公告)号：US20160211364A1

公开(公告)日：2016-07-21

申请号：US14970158

申请日：2015-12-15

Applicant: MaxPower Semiconductor, Inc.

Inventor： Jun Zeng ,  Mohamed N. Darwish

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7813 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734

Abstract: Power devices, and related process, where both gate and field plate trenches have multiple stepped widths, using self-aligned process steps.

Abstract translation: 功率器件和相关工艺，其中栅极和场板沟槽都具有多个阶梯宽度，采用自对准工艺步骤。

公开(公告)号：US20150108565A1

公开(公告)日：2015-04-23

申请号：US14523492

申请日：2014-10-24

Applicant: MaxPower Semiconductor, Inc.

Inventor： Mohamed N. Darwish ,  Jun Zeng ,  Richard A. Blanchard

IPC: H01L29/78 ,  H01L29/40

CPC classification number: H01L29/7393 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/402 ,  H01L29/407 ,  H01L29/408 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/7816

Abstract: Power semiconductor devices, and related methods, where majority carrier flow is divided into paralleled flows through two drift regions of opposite conductivity types.

Abstract translation: 功率半导体器件和相关方法，其中多数载流子流被分成平行的流经两个相反导电类型的漂移区域。

公开(公告)号：US20140054686A1

公开(公告)日：2014-02-27

申请号：US13975421

申请日：2013-08-26

Applicant: MaxPower Semiconductor, Inc.

Inventor： Mohamed N. Darwish ,  Jun Zeng

IPC: H01L29/40 ,  H01L29/78

CPC classification number: H01L29/7811 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0856 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/404 ,  H01L29/407 ,  H01L29/408 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/7813 ,  H01L29/7823 ,  H01L29/7827 ,  H01L29/7835 ,  H03K17/687

Abstract: N-channel power semiconductor devices in which an insulated field plate is coupled to the drift region, and immobile electrostatic charge is also present at the interface between the drift region and the insulation around the field plate. The electrostatic charge permits OFF-state voltage drop to occur near the source region, in addition to the voltage drop which occurs near the drain region (due to the presence of the field plate).

Abstract translation: 其中绝缘场板耦合到漂移区的N沟道功率半导体器件，并且固定静电电荷也存在于漂移区和场板周围的绝缘体之间的界面处。 除了在漏极区附近发生的电压降（由于场板的存在）外，静电电荷还允许在源极区域附近发生OFF状态电压降。

公开(公告)号：US20140042535A1

公开(公告)日：2014-02-13

申请号：US13758689

申请日：2013-02-04

Applicant: MaxPower Semiconductor, Inc.

Inventor： Mohamed N. Darwish ,  Jun Zeng ,  Richard A. Blanchard

IPC: H01L27/088 ,  H01L29/78

CPC classification number: H01L29/66734 ,  H01L21/26506 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/36 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/7395 ,  H01L29/7803 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7831 ,  H01L29/7835

Abstract: Methods and systems for power semiconductor devices integrating multiple trench transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.

Abstract translation: 用于在单个芯片上集成多个沟槽晶体管的功率半导体器件的方法和系统。 多个功率晶体管（或有源区）并联，但一个晶体管具有较低的阈值电压。 当晶体管正向偏置时，这降低了电压降。 在替代实施例中，具有较低阈值电压的功率器件简单地连接为耗尽二极管，从而分流有源晶体管的体二极管，而不会影响导通和导通状态。

公开(公告)号：US20130164895A1

公开(公告)日：2013-06-27

申请号：US13709281

申请日：2012-12-10

Applicant: MaxPower Semiconductor, Inc.

Inventor： Jun Zeng ,  Mohamed N. Darwish

IPC: H01L29/78

CPC classification number: H01L29/7827 ,  H01L21/28052 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/401 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

Abstract: Methods and systems for power semiconductor devices and structures with silicide cladding on both gates and field plates. Sidewall spacers, e.g. of silicon nitride, avoid lateral shorts or leakage between the gate silicide and the source region. A source metallization makes lateral contact to the shallow n++ source, and also makes contact to the field plate silicide and the p+ body contact region.

Abstract translation: 用于功率半导体器件和在栅极和场板上具有硅化物包层的结构的方法和系统。 侧壁间隔物，例如 的氮化硅，避免栅极硅化物和源极区域之间的横向短路或泄漏。 源极金属化使得与浅n ++源的横向接触，并且还与场板硅化物和p +体接触区域接触。