公开(公告)号：US20250151275A1

公开(公告)日：2025-05-08

申请号：US19018707

申请日：2025-01-13

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Kamal M. Karda ,  Albert Fayrushin ,  Yingda Dong

IPC: H10B43/27 ,  H10B41/27 ,  H10D30/68 ,  H10D30/69 ,  H10D64/01

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell included in a memory cell string; the memory cell including charge storage structure and channel structure separated from the charge storage structure by a dielectric structure; a first control gate associated with the memory cell and located on a first side of the charge storage structure and a first side of the channel structure; and a second control gate associated with the memory cell and electrically separated from the first control gate, the second control gate located on a second side of the charge storage structure and a second side of the channel structure.

公开(公告)号：US12279434B2

公开(公告)日：2025-04-15

申请号：US17662982

申请日：2022-05-11

Applicant: Micron Technology, Inc.

Inventor： Albert Fayrushin ,  Kamal Karda ,  Gianpietro Carnevale ,  Aurelio Giancarlo Mauri

IPC: H10B51/20 ,  H10B51/30

Abstract: Methods, systems, and devices for NAND structures with polarized materials are described. A memory device may include a polarized dielectric material located relatively near to a channel, which may reduce interference between cells. The polarized dielectric material may include a dielectric material with a fixed polarity and having a first surface with a negative polarity oriented towards the channel. The negative polarity of the polarized dielectric material may affect an electron distribution of the channel by shifting the electron distribution closer to an associated charge trapping material. The shifted electron distribution may reduce an effect of an electric field of any aggressor cells of the memory device on one or more victim cells, by creating a more uniform channel electron distribution and increasing gate control relative to a channel without the effects of the polarized dielectric material.

公开(公告)号：US20250081460A1

公开(公告)日：2025-03-06

申请号：US18745922

申请日：2024-06-17

Applicant: Micron Technology, Inc.

Inventor： Albert Fayrushin ,  Haitao Liu ,  Kunal R. Parekh

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: A microelectronic device includes a stack structure, a cell pillar structure, doped semiconductor material, and control logic devices. The stack structure includes vertically neighboring tiers respectively including a conductive structure and an insulative structure vertically neighboring the conductive structure. The cell pillar structure vertically extends through the stack structure and includes a fill material, a channel material horizontally surrounding the fill material, and an outer material stack horizontally surrounding the channel material. The doped semiconductor material vertically overlies the stack structure and includes a first portion substantially continuously horizontally extending over the stack structure and the cell pillar structure, and a second portion vertically projecting from the first portion and in physical contact with the channel material of the cell pillar structure. The control logic devices vertically underlie and are coupled to the cell pillar structures. Related methods, memory devices, and electronic systems are also described.

公开(公告)号：US20240244845A1

公开(公告)日：2024-07-18

申请号：US18622671

申请日：2024-03-29

Applicant: Micron Technology, Inc.

Inventor： Yifen Liu ,  Yan Song ,  Albert Fayrushin ,  Naiming Liu ,  Yingda Dong ,  George Matamis

IPC: H10B43/27 ,  H01L23/522 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: An electronic device comprises a stack of alternating dielectric materials and conductive materials, a pillar region extending vertically through the stack, an oxide material within the pillar region and laterally adjacent to the dielectric materials and the conductive materials of the stack, and a storage node laterally adjacent to the oxide material and within the pillar region. A charge confinement region of the storage node is in horizontal alignment with the conductive materials of the stack. A height of the charge confinement region in a vertical direction is less than a height of a respective, laterally adjacent conductive material of the stack in the vertical direction. Related methods and systems are also disclosed.

公开(公告)号：US11790991B2

公开(公告)日：2023-10-17

申请号：US17888041

申请日：2022-08-15

Applicant: Micron Technology, Inc.

Inventor： Albert Fayrushin ,  Augusto Benvenuti ,  Akira Goda ,  Luca Laurin ,  Haitao Liu

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26

CPC classification number: G11C16/08 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26

Abstract: Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a memory cell string having first, second, third, fourth, and fifth memory cells; access lines including first, second, third, fourth, and fifth access lines coupled to the first, second, third, fourth, and fifth memory cells, respectively, and a module. The first memory cell is between the second and third memory cells. The second memory cell is between the first and fourth memory cells. The third memory cell is between the first and fifth memory cells. The module is to couple the first access line to a ground node at a first time of a memory operation, couple the second and third access lines to the ground node at a second time of the operation after the first time, and couple the fourth and fifth access lines to the ground node at a third time of the operation after the second time.

公开(公告)号：US20230041326A1

公开(公告)日：2023-02-09

申请号：US17397603

申请日：2021-08-09

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Albert Fayrushin ,  Matthew J. King ,  Madison D. Drake

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/78 ,  H01L29/66

Abstract: A variety of applications can include memory devices designed to provide enhanced gate-induced-drain-leakage (GIDL) current during memory erase operations. The enhanced operation can be provided by enhancing the electric field in the channel structures of select gate transistors to strings of memory cells. The channel structures can be implemented as a segmented portion for drains and a portion opposite a gate. The segmented portion includes one or more fins and one or more non-conductive regions with both fins and non-conductive regions extending vertically from the portion opposite the gate. Variations of a border region for the portion opposite the gate with the segmented portion can include fanged regions extending from the fins into the portion opposite the gate or rounded border regions below the non-conductive regions. Such select gate transistors can be formed using a single photo mask process. Additional devices, systems, and methods are discussed.

公开(公告)号：US20220367512A1

公开(公告)日：2022-11-17

申请号：US17869732

申请日：2022-07-20

Applicant: Micron Technology, Inc.

Inventor： S.M. Istiaque Hossain ,  Prakash Rau Mokhna Rau ,  Arun Kumar Dhayalan ,  Damir Fazil ,  Joel D. Peterson ,  Anilkumar Chandolu ,  Albert Fayrushin ,  George Matamis ,  Christopher Larsen ,  Rokibul Islam

IPC: H01L27/11582 ,  G11C5/02 ,  H01L21/768 ,  G11C16/04 ,  G11C5/06

Abstract: Some embodiments include an integrated assembly having a first deck. The first deck has first memory cell levels alternating with first insulative levels. A second deck is over the first deck. The second deck has second memory cell levels alternating with second insulative levels. A cell-material-pillar passes through the first and second decks. Memory cells are along the first and second memory cell levels and include regions of the cell-material-pillar. An intermediate level is between the first and second decks. The intermediate level includes a buffer region adjacent the cell-material-pillar. The buffer region includes a composition different from the first and second insulative materials, and different from the first and second conductive regions. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11424363B2

公开(公告)日：2022-08-23

申请号：US17170082

申请日：2021-02-08

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Kamal M. Karda ,  Albert Fayrushin

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/51 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/28 ,  H01L27/11597 ,  H01L29/792 ,  H01L27/1157 ,  H01L27/1159 ,  H01L29/66

Abstract: A programmable charge-storage transistor comprises channel material, insulative charge-passage material, charge-storage material, a control gate, and charge-blocking material between the charge-storage material and the control gate. The charge-blocking material comprises a non-ferroelectric insulator material and a ferroelectric insulator material. Arrays of elevationally-extending strings of memory cells of memory cells are disclosed, including methods of forming such. Other embodiments, including method, are disclosed.

公开(公告)号：US11362175B1

公开(公告)日：2022-06-14

申请号：US17193845

申请日：2021-03-05

Applicant: Micron Technology, Inc.

Inventor： Albert Fayrushin ,  Haitao Liu ,  Matthew J. King

IPC: H01L29/06 ,  G11C16/16 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  G11C16/04

Abstract: A variety of applications can include memory devices designed to provide enhanced gate-induced-drain-leakage (GIDL) current during memory erase operations. The enhanced operation can be provided by enhancing the electric field in the channel structures of the topmost select gate transistors to strings of memory cells upon application of a voltage to the gates of the topmost select gate transistors. This electric field can be provided by using a dissected plug as a contact to the channel structure of the topmost select gate transistor, where the dissected plug has one or more conductive regions contacting the channel structure and one or more non-conductive regions contacting the channel structure. The dissected plug can be part of a contact between the data line and the channel structure. Additional devices, systems, and methods are discussed.

公开(公告)号：US11201167B2

公开(公告)日：2021-12-14

申请号：US16704938

申请日：2019-12-05

Applicant: Micron Technology, Inc.

Inventor： Albert Fayrushin ,  Augusto Benvenuti ,  Haitao Liu ,  Xin Lan

IPC: H01L27/11582 ,  H01L29/10 ,  H01L27/11573 ,  H01L29/51 ,  H01L27/11565

Abstract: Some embodiments include a pillar which contains semiconductor material, and which extends primarily along a first direction. A cross-section through the pillar along a second direction orthogonal to the first direction is through the semiconductor material and includes a lateral periphery of the pillar configured as three-sided shape. Some embodiments include an integrated assembly having a vertical stack of alternating first and second levels. The first levels include conductive structures and the second levels are insulative. Channel-material-pillars extend through the vertical stack. Each of the channel-material-pillars has a top-down cross-section which includes a lateral periphery configured as three-sided shape of an equilateral triangle with rounded vertices.