公开(公告)号：US11244954B2

公开(公告)日：2022-02-08

申请号：US16548320

申请日：2019-08-22

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Davide Resnati ,  Paolo Tessariol ,  Richard J. Hill ,  John D. Hopkins

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L29/788 ,  H01L29/792 ,  H01L21/02

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions. High-k dielectric material is adjacent to the control gate regions and is configured as an arrangement of first vertically-extending linear segments which are vertically spaced from one another. Charge-blocking material is adjacent to the high-k dielectric material and is configured as an arrangement of second vertically-extending linear segments which are vertically spaced from one another. Charge-storage material is adjacent to the charge-blocking material and is configured as an arrangement of third vertically-extending linear segments which are vertically spaced from one another. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies and methods of forming integrated assemblies.

公开(公告)号：US20210335818A1

公开(公告)日：2021-10-28

申请号：US17369630

申请日：2021-07-07

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Richard J. Hill

IPC: H01L27/11582 ,  H01L45/00 ,  H01L21/768

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and distal regions proximate the control gate regions. The control gate regions have front surfaces, top surfaces and bottom surfaces. The top and bottoms surfaces extend back from the front surfaces. High-k dielectric material is along the control gate regions. The high-k dielectric material has first regions along the top and bottom surfaces, and has second regions along the front surfaces. The first regions are thicker than the second regions. Charge-blocking material is adjacent to the second regions of the high-k dielectric material. Charge-storage material is adjacent to the charge-blocking material. Gate-dielectric material is adjacent to the charge-storage material. Channel material is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11024644B2

公开(公告)日：2021-06-01

申请号：US16548471

申请日：2019-08-22

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Shyam Surthi ,  Jordan D. Greenlee

IPC: H01L27/11582 ,  H01L29/49 ,  H01L29/51 ,  H01L21/28 ,  H01L29/792 ,  H01L29/788 ,  H01L21/02 ,  H01L27/11556

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include terminal regions, and include nonterminal regions proximate the terminal regions. The terminal regions are vertically thicker than the nonterminal regions, and are configured as segments which are vertically stacked one atop another and which are vertically spaced from one another. Blocks are adjacent to the segments and have approximately a same vertical thickness as the segments. The blocks include high-k dielectric material, charge-blocking material and charge-storage material. Channel material extends vertically along the stack and is adjacent to the blocks. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20210057435A1

公开(公告)日：2021-02-25

申请号：US16548120

申请日：2019-08-22

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Richard J. Hill

IPC: H01L27/11582 ,  H01L21/768 ,  H01L45/00

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and distal regions proximate the control gate regions. The control gate regions have front surfaces, top surfaces and bottom surfaces. The top and bottoms surfaces extend back from the front surfaces. High-k dielectric material is along the control gate regions. The high-k dielectric material has first regions along the top and bottom surfaces, and has second regions along the front surfaces. The first regions are thicker than the second regions. Charge-blocking material is adjacent to the second regions of the high-k dielectric material. Charge-storage material is adjacent to the charge-blocking material. Gate-dielectric material is adjacent to the charge-storage material. Channel material is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20210057434A1

公开(公告)日：2021-02-25

申请号：US16547885

申请日：2019-08-22

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Richard J. Hill ,  Byeung Chul Kim ,  Akira Goda

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/51 ,  H01L21/28 ,  H01L29/49 ,  H01L29/788 ,  H01L29/792

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and second regions proximate to the control gate regions. High-k dielectric material wraps around ends of the control gate regions, and is not along the second regions. Charge-blocking material is adjacent to the high-k dielectric material. Charge-storage material is adjacent to the charge-blocking material. The charge-storage material is configured as segments which are vertically stacked one atop another, and which are vertically spaced from one another by gaps. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies, and methods of forming integrated assemblies.

公开(公告)号：US20150332913A1

公开(公告)日：2015-11-19

申请号：US14802904

申请日：2015-07-17

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi

IPC: H01L21/02 ,  C23C16/46 ,  C23C16/455

CPC classification number: H01L21/31612 ,  C23C16/402 ,  C23C16/45544 ,  C23C16/45546 ,  C23C16/46 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/0228 ,  H01L21/3141

Abstract: Some embodiments include methods for semiconductor processing. A semiconductor substrate may be placed within a reaction chamber. The semiconductor substrate may have an inner region and an outer region laterally outward of said inner region, and may have a deposition surface that extends across the inner and outer regions. The semiconductor substrate may be heated by radiating thermal energy from the outer region to the inner region. The heating may eventually achieve thermal equilibrium. However, before thermal equilibrium of the outer and inner regions is reached, and while the outer region is warmer than the inner region, at least two reactants are sequentially introduced into the reaction chamber. The reactants may together form a single composition on the deposition surface through a quasi-ALD process.

Abstract translation: 一些实施例包括用于半导体处理的方法。 半导体衬底可以放置在反应室内。 半导体衬底可以具有在所述内部区域的横向外侧的内部区域和外部区域，并且可以具有延伸穿过内部区域和外部区域的沉积表面。 可以通过从外部区域向内部区域辐射热能来加热半导体衬底。 加热可能最终实现热平衡。 然而，在达到外部和内部区域的热平衡之前，并且当外部区域比内部区域更热时，至少两个反应物被顺序地引入反应室。 反应物可以通过准ALD工艺在沉积表面上一起形成单一的组合物。

公开(公告)号：US20150255599A1

公开(公告)日：2015-09-10

申请号：US14718785

申请日：2015-05-21

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7827 ,  H01L21/76232 ,  H01L21/764 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/4236 ,  H01L29/66666

Abstract: Vertical memory devices comprise vertical transistors, buried digit lines extending in a first direction in an array region, and word lines extending in a second direction different from the first direction. Portions of the word lines in a word line end region have a first vertical length greater than a second vertical length of portions of the word lines in the array region. Apparatuses including vertical transistors in an array region, buried digit lines extending in a first direction, and word lines are also disclosed. Each of the word lines extends in a second direction perpendicular to the first direction, is formed over at least a portion of a sidewall of at least some of the vertical transistors, and vertically has a depth in a word line end region about equal to or greater than a depth thereof in the array region.

Abstract translation: 垂直存储器件包括垂直晶体管，在阵列区域中沿第一方向延伸的掩埋数字线以及沿与第一方向不同的第二方向延伸的字线。 字线端区域中的字线的部分具有大于阵列区域中的字线的部分的第二垂直长度的第一垂直长度。 还公开了包括阵列区域中的垂直晶体管，在第一方向上延伸的埋入数字线以及字线的装置。 每个字线在垂直于第一方向的第二方向上延伸，形成在至少一些垂直晶体管的侧壁的至少一部分上方，并且在字线端部区域中垂直地具有大约等于或等于 大于其在阵列区域中的深度。

公开(公告)号：US09054216B2

公开(公告)日：2015-06-09

申请号：US14319201

申请日：2014-06-30

Applicant: Micron Technology, Inc.

Inventor： Jaydip Guha ,  Shyam Surthi ,  Suraj J. Mathew ,  Kamal M. Karda ,  Hung-Ming Tsai

IPC: H01L21/8238 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/108 ,  H01L29/66 ,  H01L29/417 ,  H01L27/11

CPC classification number: H01L21/823487 ,  H01L27/108 ,  H01L27/10876 ,  H01L27/1104 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833

Abstract: Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed.

Abstract translation: 沟槽形成半导体材料。 遮蔽材料横向形成在沟槽的至少垂直内侧壁部分上。 电导率改性杂质通过沟槽的基底注入到下面的半导体材料中。 这种杂质被扩散到横向覆盖在沟槽的顶部内侧壁部分上的掩蔽材料中，并且被扩散到半导体材料中，该半导体材料被容纳在中间通道部分下方的沟槽之间。 在中间通道部分下方的半导体材料中形成一个正面内部源极/漏极。 内部源极/漏极部分包括在其中具有杂质的沟槽之间的所述半导体材料。 导电线横向形成并电耦合到内源/漏的相对侧中的至少一个。 栅极形成在导电线的正上方并与导电线隔开并且横向邻近中间通道部分。 公开了其他实施例。

公开(公告)号：US12237013B2

公开(公告)日：2025-02-25

申请号：US17372891

申请日：2021-07-12

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Matthew Thorum

IPC: H01L23/532 ,  G11C16/04 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating first and second levels. A panel extends through the stack. The first levels have proximal regions adjacent the panel, and have distal regions further from the panel than the proximal regions. The distal regions include conductive structures. The conductive structures have a first thickness. The proximal regions include insulative structures. The insulative structures have a second thickness at least about as large as the first thickness. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20240395325A1

公开(公告)日：2024-11-28

申请号：US18647354

申请日：2024-04-26

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  James E. Davis ,  Kenneth W. Marr

IPC: G11C16/04 ,  H01L23/528 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35 ,  H10B99/00

Abstract: A semiconductor device including a substrate; a substrate; a memory array disposed on the substrate, the memory array including one or more memory planes, and a plurality of source region contact (SRC) nodes that are disposed on a backside surface of corresponding one of the one or more memory planes and above the substrate; a plurality of high-voltage (HV) diodes that are disposed in the substrate and that are connected to corresponding SRC nodes, the HV diodes including a first type dopant material; and a plurality of highly doped regions that are disposed in the substrate and that include a second type dopant material, each of the plurality of highly doped regions including a plurality of local maximum doping regions that are vertically aligned under a frontside surface of the substrate.