公开(公告)号：US08582708B2

公开(公告)日：2013-11-12

申请号：US13344201

申请日：2012-01-05

申请人： Michiyo Yamamoto ,  Kenji Murata ,  Kazuya Hatooka

发明人： Michiyo Yamamoto ,  Kenji Murata ,  Kazuya Hatooka

IPC分类号： H04L7/00

CPC分类号： H04L7/0337 ,  H03L7/091 ,  H03L7/0996

摘要： A clock and data recovery circuit includes a multiphase clock generator circuit which generates a multiphase clock having a plurality of clocks, a sampling circuit which samples a received data signal transferring serial data in synchronism with each of the plurality of clocks, and generates a plurality of data signals, a data recovery unit which generates a selection signal indicating a data signal having an appropriate phase among the plurality of data signals, and a storage unit which stores the selection signal. The data recovery unit selects one of the plurality of data signals, based on the selection signal read from the storage unit, and a clock corresponding to the selected data signal.

摘要翻译： 时钟和数据恢复电路包括产生具有多个时钟的多相时钟的多相时钟发生器电路，采样电路，对与多个时钟中的每个时钟同步地传送串行数据的接收数据信号进行采样，并产生多个 数据信号，数据恢复单元，其生成指示在多个数据信号中具有适当相位的数据信号的选择信号;以及存储单元，存储选择信号。 数据恢复单元基于从存储单元读取的选择信号和对应于所选择的数据信号的时钟来选择多个数据信号中的一个。

公开(公告)号：US08085101B2

公开(公告)日：2011-12-27

申请号：US12678630

申请日：2008-10-28

申请人： Michiyo Yamamoto ,  Tsuyoshi Ebuchi ,  Kenji Murata

发明人： Michiyo Yamamoto ,  Tsuyoshi Ebuchi ,  Kenji Murata

IPC分类号： H03B29/00

CPC分类号： H03L7/183 ,  H03B5/1206 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1265 ,  H03B2200/005 ,  H03L7/087 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/099 ,  H03L7/0995 ,  H03L7/107 ,  H03L2207/06

摘要： A spread spectrum controller (20) controls a PLL (10) so that the PLL outputs a spread-spectrum processed clock signal. A loop bandwidth controller (30) controls at least one of a phase detector (11), a loop filter (12), a voltage-controlled oscillator (13), and a frequency divider (14) in the PLL (10) during operation of the spread spectrum controller (20) to change a loop bandwidth of the PLL (10).

摘要翻译： 扩频控制器（20）控制PLL（10），使得PLL输出扩频处理的时钟信号。 环路带宽控制器（30）在操作期间控制PLL（10）中的相位检测器（11），环路滤波器（12），压控振荡器（13）和分频器（14）中的至少一个 扩展频谱控制器（20）改变PLL（10）的环路带宽。

公开(公告)号：US08034908B2

公开(公告)日：2011-10-11

申请号：US12760793

申请日：2010-04-15

申请人： Hirokazu Annoura ,  Kenji Murata ,  Takashi Yamamura

发明人： Hirokazu Annoura ,  Kenji Murata ,  Takashi Yamamura

IPC分类号： C07J9/00 ,  C07H17/02 ,  A01N43/04 ,  A61K31/70

CPC分类号： C07D317/28 ,  C07C247/04 ,  C07H15/04 ,  C07H15/26

摘要： Novel glycolipid derivatives, where the substituent of the sphingosine base part is a short carbon chain alkyl group, substituted or unsubstituted cycloalkyl group, substituted or unsubstituted aryl group or substituted or unsubstituted aralkyl group and efficient synthetic methods for practical mass production of the same and intermediates useful for the synthesis of these compounds.Glycolipids having the formula (I): where R3 indicates a substituted or unsubstituted C1 to C7 linear alkyl group, substituted or unsubstituted cycloalkyl group, substituted or unsubstituted aryl group, or substituted or unsubstituted aralkyl group and R8 indicates a substituted or unsubstituted C1 to C35 alkyl group, substituted or unsubstituted aryl group or substituted or unsubstituted aralkyl group are chemically synthesized.

摘要翻译： 新型糖脂衍生物，其中鞘氨醇碱基部分的取代基为短碳链烷基，取代或未取代的环烷基，取代或未取代的芳基或取代或未取代的芳烷基，以及用于实际大量生产其的中间体的有效合成方法 可用于合成这些化合物。 具有式（I）的糖脂：其中R3表示取代或未取代的C1至C7直链烷基，取代或未取代的环烷基，取代或未取代的芳基或取代或未取代的芳烷基，R8表示取代或未取代的C1至C35 烷基，取代或未取代的芳基或取代或未取代的芳烷基是化学合成的。

公开(公告)号：US07986256B2

公开(公告)日：2011-07-26

申请号：US12377989

申请日：2007-08-10

申请人： Michiyo Yamamoto ,  Kenji Murata ,  Masakazu Shigemori

发明人： Michiyo Yamamoto ,  Kenji Murata ,  Masakazu Shigemori

IPC分类号： H03M1/12

CPC分类号： H03M1/1245 ,  H03M1/365

摘要： An external input operation clock signal is required for operating a conventional A/D converter, and the performance of the A/D converter is undesirably determined by the characteristics of the external input operation clock. A clock generator circuit for automatically generating an operation clock is provided inside an A/D converter to make the A/D converter require no external input operation clock. Further, a circuit for detecting the operation times of the constituents of the A/D converter is provided to generate a clock with which the A/D converter is optimally operated, thereby realizing high-speed operation and low power consumption.

摘要翻译： 操作常规A / D转换器需要外部输入操作时钟信号，并且A / D转换器的性能不合需要地由外部输入操作时钟的特性决定。 在A / D转换器内部设置用于自动生成工作时钟的时钟发生器电路，使A / D转换器不需要外部输入操作时钟。 此外，提供用于检测A / D转换器的组成部分的操作时间的电路，以产生A / D转换器被最佳操作的时钟，从而实现高速操作和低功耗。

公开(公告)号：US20110099912A1

公开(公告)日：2011-05-05

申请号：US12593645

申请日：2008-03-28

申请人： Yasuhiro Ohtake ,  Kenji Murata ,  Shigenobu Ohsawa ,  Jiro Yoshihara

发明人： Yasuhiro Ohtake ,  Kenji Murata ,  Shigenobu Ohsawa ,  Jiro Yoshihara

IPC分类号： B60J5/04

CPC分类号： B60J5/0402 ,  B60J10/21 ,  B60J10/86 ,  B60J10/88

摘要： A vehicle door frame structure has an upper sash member located along a roof panel of a vehicle body and also has a vertical pillar sash member located along a center pillar of the vehicle body. The upper sash member has, at its linear end joined to the vertical pillar sash member side, an aesthetically designed section and an inner frame portion. The aesthetically designed section is located on the outer side of the door, and the inner frame portion is located closer to the vehicle interior than the aesthetically designed section and is shorter in length than the aesthetically designed section. The vertical pillar sash member has at its upper end a superposed contact section that is superposed, in the direction of the thickness of the door, on an end of the inner frame portion of the upper sash member, and the superposed contact section and the inner frame portion are joined together while being superposed on each other.

摘要翻译： 车门框架结构具有沿着车身的车顶板定位的上框架构件，并且还具有沿着车身的中心柱定位的立柱框架构件。 上框架构件在其直线端部处连接到垂直支撑框架构件侧，具有美观设计的部分和内框架部分。 美观设计的部分位于门的外侧，并且内框架部分位于比美观设计的部分更靠近车辆内部并且比美观设计的部分的长度更短。 立柱框架构件的上端具有重叠的接触部分，其在门的厚度方向上重叠在上框架构件的内框架部分的端部上，并且叠置的接触部分和内部 框架部分彼此叠合在一起。

公开(公告)号：US07834794B2

公开(公告)日：2010-11-16

申请号：US12439444

申请日：2007-08-10

申请人： Masakazu Shigemori ,  Koji Sushihara ,  Kenji Murata

发明人： Masakazu Shigemori ,  Koji Sushihara ,  Kenji Murata

IPC分类号： H03M1/12

CPC分类号： H03M1/0624 ,  H03M1/206 ,  H03M1/365

摘要： The conventional A/D converter has a drawback that the conversion precision is degraded when the operation periods of the constituents of the A/D converter are shortened due to the duty ratio of an external input clock because the operation periods of the constituents of the A/D converter depend on the pulse width of the external input clock. However, a highly-precise A/D conversion operation independent of the duty ratio of the external input clock can be realized by providing a circuit for detecting the operation periods of the constituents of the A/D converter, and adjusting the duty ratio of the operation clock according to the detected operation periods of the constituents of the A/D converter.

摘要翻译： 传统的A / D转换器具有这样的缺点，即当A / D转换器的构成要素的操作周期由于外部输入时钟的占空比而缩短时，转换精度降低，因为A / D转换器取决于外部输入时钟的脉冲宽度。 然而，与外部输入时钟的占空比无关的高精度A / D转换操作可以通过提供用于检测A / D转换器的构成要素的操作周期的电路来实现，并且调整占空比 根据检测到的A / D转换器的构成要素的运行时间来设定运转时钟。

公开(公告)号：US07777293B2

公开(公告)日：2010-08-17

申请号：US10898965

申请日：2004-07-27

申请人： Yoshinori Miyada ,  Kenji Murata ,  Daisuke Nomasaki

发明人： Yoshinori Miyada ,  Kenji Murata ,  Daisuke Nomasaki

IPC分类号： H01L29/93

CPC分类号： H01L27/0805 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit has a plurality of capacitor cells, and each capacitor cell has an upper electrode and a lower electrode. These electrodes are respectively connected to an upper electrode wiring and a lower electrode. When, for example, the upper electrode is connected to the upper electrode wiring and the electrode wiring is located at a side of the lower electrode of another capacitor cell or a side of the lower electrode wiring connecting these electrodes, a shield wiring is provided between the upper electrode wiring and the adjacently-located lower electrode of the other capacitor cell or between the upper electrode wiring and the adjacently-located lower electrode wiring. Thus, with this shield wiring, the capacitance coupling between each wiring of the capacitor cells and each upper electrode or each lower electrode of the capacitor cells are effectively suppressed.

摘要翻译： 半导体集成电路具有多个电容器单元，并且每个电容器单元具有上电极和下电极。 这些电极分别连接到上电极布线和下电极。 当例如上电极连接到上电极布线并且电极布线位于另一个电容器单元的下电极的一侧或连接这些电极的下电极布线的一侧时，屏蔽布线设置在 上电极布线和另一个电容器单元的相邻位置的下电极或上电极布线和相邻位置的下电极布线之间。 因此，利用该屏蔽布线，可以有效地抑制电容器单元的各布线与电容器单元的每个上电极或每个下电极之间的电容耦合。

公开(公告)号：USD598010S1

公开(公告)日：2009-08-11

申请号：US29292765

申请日：2007-10-25

申请人： Takeshi Matsuda ,  Kenji Hatano ,  Masaji Komuro ,  Kenji Murata

设计人： Takeshi Matsuda ,  Kenji Hatano ,  Masaji Komuro ,  Kenji Murata

公开(公告)号：US06927723B2

公开(公告)日：2005-08-09

申请号：US10855397

申请日：2004-05-28

申请人： Daisuke Nomasaki ,  Kenji Murata ,  Hideki Tanaka ,  Yoshinori Miyada

发明人： Daisuke Nomasaki ,  Kenji Murata ,  Hideki Tanaka ,  Yoshinori Miyada

IPC分类号： H03M1/12 ,  H03M1/46

CPC分类号： H03M1/124 ,  H03M1/468

摘要： In a charge redistribution type A/D converter, an input-side capacitor terminal and a comparator-side capacitor terminal are connected through first and second analog switches to a fixed-voltage supply circuit, and the input-side capacitor terminal is connected through a third analog switch to the outside. Immediately before sampling an analog signal, the first and second analog switches are closed while the third analog switch is opened, according to a RESET signal. Thereby, fixed voltages are supplied to the input-side capacitor terminal and the comparator-side capacitor terminal, respectively, and charge stored in a weighting capacitor unit is initialized to a predetermined value.

摘要翻译： 在电荷再分配型A / D转换器中，输入侧电容器端子和比较器侧电容器端子通过第一和第二模拟开关连接到固定电压电源电路，并且输入侧电容器端子通过 第三个模拟开关到外面。 在采样模拟信号之前，根据RESET信号，第三模拟开关打开时，第一和第二模拟开关闭合。 由此，固定电压分别被提供给输入侧电容器端子和比较器侧电容器端子，并将存储在加权电容器单元中的电荷初始化为预定值。

公开(公告)号：US20050001291A1

公开(公告)日：2005-01-06

申请号：US10898965

申请日：2004-07-27

申请人： Yoshinori Miyada ,  Kenji Murata ,  Daisuke Nomasaki

发明人： Yoshinori Miyada ,  Kenji Murata ,  Daisuke Nomasaki

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L23/522 ,  H01L27/08 ,  H01L23/552

CPC分类号： H01L27/0805 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit has a plurality of capacitor cells, and each capacitor cell has an upper electrode and a lower electrode. These electrodes are respectively connected to an upper electrode wiring and a lower electrode. When, for example, the upper electrode is connected to the upper electrode wiring and the electrode wiring is located at a side of the lower electrode of another capacitor cell or a side of the lower electrode wiring connecting these electrodes, a shield wiring is provided between the upper electrode wiring and the adjacently-located lower electrode of the other capacitor cell or between the upper electrode wiring and the adjacently-located lower electrode wiring. Thus, with this shield wiring, the capacitance coupling between each wiring of the capacitor cells and each upper electrode or each lower electrode of the capacitor cells are effectively suppressed.

摘要翻译： 半导体集成电路具有多个电容器单元，并且每个电容器单元具有上电极和下电极。 这些电极分别连接到上电极布线和下电极。 当例如上电极连接到上电极布线并且电极布线位于另一个电容器单元的下电极的一侧或连接这些电极的下电极布线的一侧时，屏蔽布线设置在 上电极布线和另一个电容器单元的相邻位置的下电极或上电极布线和相邻位置的下电极布线之间。 因此，利用该屏蔽布线，可以有效地抑制电容器单元的各布线与电容器单元的每个上电极或每个下电极之间的电容耦合。