公开(公告)号：US20180218518A1

公开(公告)日：2018-08-02

申请号：US15422359

申请日：2017-02-01

Applicant: NVIDIA Corporation

Inventor： Zhou Yan ,  Franciscus Wilhelmus Sijstermans ,  Yuanzhi Hua ,  Xiaojun Wang ,  Jeffrey Michael Pool ,  William J. Dally ,  Liang Chen

IPC: G06T9/00 ,  G06T1/20 ,  G06T1/60

CPC classification number: G06T9/002 ,  G06T1/20 ,  G06T1/60

Abstract: A method, computer program product, and system for sparse convolutional neural networks that improves efficiency is described. Multi-bit data for input to a processing element is received at a compaction engine. The multi-bit data is determined to equal zero and a single bit signal is transmitted from the memory interface to the processing element in lieu of the multi-bit data, where the single bit signal indicates that the multi-bit data equals zero. A compacted data sequence for input to a processing element is received by a memory interface. The compacted data sequence is transmitted from the memory interface to an expansion engine. Non-zero values are extracted from the compacted data sequence and zeros are inserted between the non-zero values by the expansion engine to generate an expanded data sequence that is output to the processing element.

公开(公告)号：US20170279355A1

公开(公告)日：2017-09-28

申请号：US15080461

申请日：2016-03-24

Applicant: NVIDIA Corporation

Inventor： Sudhir Shrikantha Kudva ,  William J. Dally ,  Thomas Hastings Greer, III ,  Carl Thomas Gray

IPC: H02M3/158 ,  H02M1/08

CPC classification number: H02M3/158 ,  H02M1/08 ,  H02M3/156 ,  H02M2001/0009 ,  H02M2001/0019 ,  H02M2003/1566

Abstract: A system and method are provided for controlling a modified buck converter circuit. A pull-up switching mechanism that is coupled to an upstream terminal of an inductor within a modified buck converter circuit is enabled. A load current at the output of the modified buck regulator circuit is measured. A capacitor current associated with a capacitor that is coupled to a downstream terminal of the inductor is continuously sensed and the pull-up switching mechanism is disabled when the capacitor current is greater than a sum of the load current and an enabling current value.

公开(公告)号：US09235392B2

公开(公告)日：2016-01-12

申请号：US14161617

申请日：2014-01-22

Applicant: NVIDIA Corporation

Inventor： William J. Dally

IPC: G06F9/44 ,  G06F9/45

CPC classification number: G06F8/4432 ,  Y02D10/41

Abstract: A system, method, and computer program product are provided for compiling a computer program comprising arithmetic operations having different requirements with respect to numeric dynamic range, numeric resolution, or any combination thereof. The method comprises generating a transformed graph representation of the computer program by applying propagation rules that provide for relaxed numeric requirements, where applicable, and generating output code based on the transformed graph representation. Relaxing numeric requirements, such as dynamic range and resolution requirements, may advantageously lower power consumption during execution of the computer program.

Abstract translation: 提供了一种系统，方法和计算机程序产品，用于编译包括关于数字动态范围，数字分辨率或其任何组合具有不同要求的算术运算的计算机程序。 该方法包括通过应用传播规则来生成计算机程序的变换图表示，该传播规则在适用的情况下提供放松的数字要求，并且基于变换的图表示产生输出代码。 轻松的数字要求（例如动态范围和分辨率要求）可有利地降低计算机程序执行期间的功耗。

公开(公告)号：US09208900B2

公开(公告)日：2015-12-08

申请号：US14147411

申请日：2014-01-03

Applicant: NVIDIA Corporation

Inventor： Mahmut Ersin Sinangil ,  William J. Dally

IPC: G11C29/00 ,  G11C29/52 ,  G11C7/12 ,  G11C8/08 ,  G11C11/417 ,  G11C11/418 ,  G11C11/419 ,  G11C29/44

CPC classification number: G11C29/52 ,  G11C7/12 ,  G11C8/08 ,  G11C11/417 ,  G11C11/418 ,  G11C11/419 ,  G11C2029/4402

Abstract: A method and a system are provided for performing address-based memory access assist. An address is received for a memory access and a determination is made, based on the address, that access assist is enabled for at least one storage cell corresponding to the address. The access assist is applied to the at least one storage cell to perform the memory access.

Abstract translation: 提供了一种用于执行基于地址的存储器访问辅助的方法和系统。 接收用于存储器访问的地址，并且基于该地址确定对与该地址相对应的至少一个存储单元启用该访问辅助。 访问辅助被应用于至少一个存储单元以执行存储器访问。

公开(公告)号：US09153539B2

公开(公告)日：2015-10-06

申请号：US13973947

申请日：2013-08-22

Applicant: NVIDIA Corporation

Inventor： William J. Dally ,  Jonah M. Alben ,  John W. Poulton ,  Thomas Hastings Greer, III

IPC: G11C11/40 ,  H01L23/535 ,  G06F13/00 ,  H03K19/00

CPC classification number: H01L23/535 ,  G06F13/00 ,  G06F13/4072 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/13091 ,  H01L2924/15192 ,  H01L2924/15311 ,  H03K19/00 ,  Y02D10/14 ,  Y02D10/151 ,  H01L2924/00

Abstract: A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a graphics processing cluster (GPC) chip, and an MCM package configured to include the first processor chip, the GPC chip, and an interconnect circuit. The first processor chip is configured to include a first ground-referenced single-ended signaling interface circuit. A first set of electrical traces fabricated within the MCM package and configured to couple the first single-ended signaling interface circuit to the interconnect circuit. The GPC chip is configured to include a second single-ended signaling interface circuit and to execute shader programs. A second set of electrical traces fabricated within the MCM package and configured to couple the second single-ended signaling interface circuit to the interconnect circuit. In one embodiment, each single-ended signaling interface advantageously implements ground-referenced single-ended signaling.

Abstract translation: 包括多芯片模块（MCM）的互连芯片的系统包括第一处理器芯片，图形处理集群（GPC）芯片和被配置为包括第一处理器芯片，GPC芯片和互连电路的MCM封装。 第一处理器芯片被配置为包括第一接地参考单端信令接口电路。 在MCM封装内制造的第一组电迹线，用于将第一单端信令接口电路耦合到互连电路。 GPC芯片被配置为包括第二单端信令接口电路并执行着色器程序。 在MCM封装内制造的第二组电迹线，用于将第二单端信令接口电路耦合到互连电路。 在一个实施例中，每个单端信令接口有利地实现接地参考的单端信令。

公开(公告)号：US09153314B2

公开(公告)日：2015-10-06

申请号：US13890899

申请日：2013-05-09

Applicant: NVIDIA Corporation

Inventor： William J. Dally

IPC: G11C11/40 ,  G11C11/4096 ,  G11C7/10

CPC classification number: G11C11/4096 ,  G11C7/1057 ,  G11C7/1069 ,  H01L2224/0401 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/15192 ,  H01L2924/15311

Abstract: A system is provided for transmitting signals. The system includes a ground-referenced single-ended signaling (GRS) driver circuit that is configured to pre-charge a first capacitor to store a first charge between a first output node and a first reference node based on a first input data signal during a first pre-charge phase and drive an output signal relative to a ground network based on the first charge during a first drive phase. A control circuit is configured to generate a first set of control signals based on the first input data signal and a first clock signal, where the first set of control signals causes the first GRS driver circuit to operate in either the first pre-charge phase or in the first drive phase.

Abstract translation: 提供用于发送信号的系统。 该系统包括接地参考单端信令（GRS）驱动器电路，其被配置为在第一输入节点和第一参考节点之间基于第一输入数据信号预先对第一电容器预充电以在第一输出节点和第一参考节点之间存储第一电荷 第一预充电阶段，并且在第一驱动阶段期间基于第一充电来驱动相对于地面网络的输出信号。 控制电路被配置为基于第一输入数据信号和第一时钟信号产生第一组控制信号，其中第一组控制信号使第一GRS驱动电路在第一预充电阶段或第 在第一个驱动阶段。

公开(公告)号：US09077329B2

公开(公告)日：2015-07-07

申请号：US14151715

申请日：2014-01-09

Applicant: NVIDIA Corporation

Inventor： Ilyas Elkin ,  William J. Dally ,  Jonah M. Alben

IPC: H03K3/356

CPC classification number: H03K3/356 ,  H03K3/356026 ,  H03K3/356052 ,  H03K3/356147 ,  H03K3/356191

Abstract: One embodiment of the present invention sets forth a technique for capturing and holding a level of an input signal using a latch circuit that presents a low number of loads to the clock signal. The clock is only coupled to a bridging transistor and a pair of clock-activated pull-down or pull-up transistors. The level of the input signal is propagated to the output signal when the storage sub-circuit is not enabled. The storage sub-circuit is enabled by the bridging transistor and a propagation sub-circuit is activated and deactivated by the pair of clock-activated transistors.

Abstract translation: 本发明的一个实施例提出了一种使用向时钟信号呈现低负载的锁存电路来捕获和保持输入信号电平的技术。 时钟仅耦合到桥接晶体管和一对时钟激活的下拉或上拉晶体管。 当存储子电路未使能时，输入信号的电平被传播到输出信号。 存储子电路由桥接晶体管使能，传播子电路由一对时钟激活晶体管激活和去激活。

公开(公告)号：US09058453B2

公开(公告)日：2015-06-16

申请号：US13902701

申请日：2013-05-24

Applicant: NVIDIA Corporation

Inventor： Stephen William Keckler ,  William J. Dally ,  Steven Lee Scott ,  Brucek Kurdo Khailany ,  Michael Allen Parker

IPC: G06F17/50

CPC classification number: G06F13/409 ,  G06F13/1668 ,  G06F13/4068 ,  G06F17/5054

Abstract: A system and method are provided for configuring a plurality of pin resources. The method includes identifying a plurality of pin resources of a primary application specific integrated circuit (ASIC) device and configuring the plurality of pin resources based on a pin distribution between a first interface and a second interface, where the first interface provides a first communication path between the primary ASIC device and a first device, and the second interface provides a second communication path between the primary ASIC device and a second device.

Abstract translation: 提供了一种用于配置多个引脚资源的系统和方法。 该方法包括识别主要专用集成电路（ASIC）设备的多个引脚资源，并且基于第一接口和第二接口之间的引脚分配来配置多个引脚资源，其中第一接口提供第一通信路径 在主ASIC设备和第一设备之间，并且第二接口提供主ASIC设备和第二设备之间的第二通信路径。

公开(公告)号：US20140380002A1

公开(公告)日：2014-12-25

申请号：US13922189

申请日：2013-06-19

Applicant: NVIDIA Corporation

Inventor： William J. Dally ,  James David Balfour ,  Ignacio Llamas Ubieto

IPC: G06F12/00

CPC classification number: G06F9/466

Abstract: A system, method, and computer program product are provided for accessing a queue. The method includes receiving a first request to reserve a data record entry in a queue, updating a queue state block based on the first request, and returning a response to the request. A second request is received to commit the data record entry and the queue state block is updated based on the second request.

Abstract translation: 提供了用于访问队列的系统，方法和计算机程序产品。 该方法包括接收第一请求以在队列中保留数据记录条目，基于第一请求更新队列状态块，并返回对该请求的响应。 接收到提交数据记录条目的第二请求，并且基于第二请求更新队列状态块。

公开(公告)号：US20140351780A1

公开(公告)日：2014-11-27

申请号：US13902701

申请日：2013-05-24

Applicant: Nvidia Corporation

Inventor： Stephen William Keckler ,  William J. Dally ,  Steven Lee Scott ,  Brucek Kurdo Khailany ,  Michael Allen Parker

IPC: G06F17/50

CPC classification number: G06F13/409 ,  G06F13/1668 ,  G06F13/4068 ,  G06F17/5054

Abstract: A system and method are provided for configuring a plurality of pin resources. The method includes identifying a plurality of pin resources of a primary application specific integrated circuit (ASIC) device and configuring the plurality of pin resources based on a pin distribution between a first interface and a second interface, where the first interface provides a first communication path between the primary ASIC device and a first device, and the second interface provides a second communication path between the primary ASIC device and a second device.

Abstract translation: 提供了一种用于配置多个引脚资源的系统和方法。 该方法包括识别主要专用集成电路（ASIC）设备的多个引脚资源，并且基于第一接口和第二接口之间的引脚分配来配置多个引脚资源，其中第一接口提供第一通信路径 在主ASIC设备和第一设备之间，并且第二接口提供主ASIC设备和第二设备之间的第二通信路径。