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    Probe card with rigid base having apertures for testing semiconductor device, and semiconductor device test method using probe card
    41.
    发明授权
    Probe card with rigid base having apertures for testing semiconductor device, and semiconductor device test method using probe card 有权
    具有用于测试半导体器件的孔的具有刚性基座的探针卡，以及使用探针卡的半导体器件测试方法

    公开(公告)号：US06433563B1

    公开(公告)日：2002-08-13

    申请号：US09417706

    申请日：1999-10-13

    申请人： Shigeyuki Maruyama

    发明人： Shigeyuki Maruyama

    IPC分类号： G01R3102

    CPC分类号： G01R1/0408 ,  G01R1/07314 ,  G01R31/2831

    摘要： The present invention relates to the testing method of a probe card and semiconductor device to conduct the testing to each chip in the wafer condition where a plurality of chips and CSPs (Chip Size Packages) are formed. The probe card is characterized by including a flexible contact board, a plurality of contact electrode groups provided in a predetermined layout on the contact board, a rigid base provided on the contact board between the contact electrode groups to have an aperture to expose the contact board of the area where the contact electrode is formed and wiring provided on the contact board and connected to the contact electrode. The advantages of the probe card is that it can always attain good contact condition of each chip and electrode pad of CSP on the occasion of testing the chip and CSP in the wafer condition.

    摘要翻译： 本发明涉及探针卡和半导体器件的测试方法，用于在形成多个芯片和CSP（芯片尺寸封装）的晶片状态下对每个芯片进行测试。 探针卡的特征在于包括柔性接触板，以接触板上的预定布置设置的多个接触电极组，设置在接触电极组之间的接触板上的刚性基座，以具有露出接触板的孔 形成接触电极的区域和设置在接触板上并连接到接触电极的布线。 探针卡的优点是在晶片状态下测试芯片和CSP时，可以始终获得CSP每个芯片和电极焊盘良好的接触条件。

    Test carrier for semiconductor integrated circuit and method of testing semiconductor integrated circuit
    43.
    发明授权
    Test carrier for semiconductor integrated circuit and method of testing semiconductor integrated circuit 失效
    半导体集成电路测试载体和半导体集成电路测试方法

    公开(公告)号：US5828224A

    公开(公告)日：1998-10-27

    申请号：US686052

    申请日：1996-07-24

    申请人： Shigeyuki Maruyama

    发明人： Shigeyuki Maruyama

    IPC分类号： G01R1/04 ,  G01R31/28 ,  G01R31/02

    CPC分类号： G01R1/0483 ,  G01R31/2886 ,  G01R31/2893

    摘要： A holding apparatus of a semiconductor device had a configuration for putting a semiconductor device as a chip or a packaged semiconductor device between a first substrate and a second substrate and fitting magnets to the first substrate and magnetic pieces to the second substrate respectively, and the first substrate and the second substrate are fixed by attraction acted between the magnets and the magnetic pieces.

    摘要翻译： 半导体装置的保持装置具有将半导体器件作为芯片或封装的半导体器件放置在第一基板和第二基板之间并且将磁体分别配合到第一基板和磁片到第二基板的配置，并且第一 基板和第二基板通过作用在磁体和磁片之间的吸引来固定。

    Electronic component attaching tool
    45.
    发明授权
    Electronic component attaching tool 有权
    电子元件连接工具

    公开(公告)号：US07430798B2

    公开(公告)日：2008-10-07

    申请号：US11126246

    申请日：2005-05-11

    申请人： Daisuke Koizumi ,  Shigeyuki Maruyama ,  Kazuhiro Tashiro ,  Naoyuki Watanabe

    发明人： Daisuke Koizumi ,  Shigeyuki Maruyama ,  Kazuhiro Tashiro ,  Naoyuki Watanabe

    IPC分类号： B23P19/00 ,  H01L21/44

    CPC分类号： B25B27/14 ,  H05K7/1061 ,  Y10T29/4913 ,  Y10T29/53174 ,  Y10T29/53178 ,  Y10T29/53183 ,  Y10T29/53187 ,  Y10T29/53191 ,  Y10T29/53943

    摘要： An electronic component attaching tool suitable for an external shape of a semiconductor device is prepared. The electronic component attaching tool has a function of aligning a position of the semiconductor device to an IC socket. The electronic component attaching tool is mounted on the standard surface that is formed on the IC socket substantially regardless of the external shape of the semiconductor device. The semiconductor device is then aligned and attached to the IC socket by using the electronic component attaching tool, and the electronic component attaching tool is removed from the IC socket. Another electronic component attaching tool suitable for an external shape of another semiconductor device is prepared, and the same procedure as the above is performed to align and attach this semiconductor device to the same type IC socket.

    摘要翻译： 准备适用于半导体器件外形的电子部件安装工具。 电子部件安装工具具有将半导体器件的位置与IC插座对准的功能。 电子部件安装工具安装在形成在IC插座上的标准表面上，基本上与半导体器件的外部形状无关。 然后通过使用电子部件安装工具将半导体器件对准并附接到IC插座，并且将电子部件附接工具从IC插座移除。 准备适用于另一半导体器件的外部形状的另一个电子部件附接工具，并且执行与上述相同的步骤以将该半导体器件对准并附接到相同类型的IC插座。

    Contactor having contact electrodes of metal springs embedded in a plate-like structure
    46.
    发明授权
    Contactor having contact electrodes of metal springs embedded in a plate-like structure 失效
    具有镶嵌在板状结构中的金属弹簧的接触电极的接触器

    公开(公告)号：US07403024B2

    公开(公告)日：2008-07-22

    申请号：US10900362

    申请日：2004-07-28

    申请人： Shigeyuki Maruyama ,  Kazuhiro Tashiro ,  Naoyuki Watanabe ,  Daisuke Koizumi ,  Takafumi Hashitani ,  Ei Yano

    发明人： Shigeyuki Maruyama ,  Kazuhiro Tashiro ,  Naoyuki Watanabe ,  Daisuke Koizumi ,  Takafumi Hashitani ,  Ei Yano

    IPC分类号： G01R31/26

    CPC分类号： G01R1/06716 ,  G01R1/06733 ,  G01R1/07357 ,  G01R3/00

    摘要： A contactor has contact electrodes elastically deformable in a direction of thickness of the contactor so that the contactor can make a contact with a semiconductor device with an appropriate contact pressure. The contactor is positioned between the semiconductor device and a test board so as to electrically connect the semiconductor device to the test board. Each of a plurality of contact electrodes has a first contact electrode part, a second contact electrode part and a connecting part electrically connecting the first contact electrode part to the second contact electrode part. The first contact electrode part contacts an electrode of the semiconductor device. The second contact electrode part contacts a terminal of the test board. A combining member has an insulating characteristic and holds the connecting part of each of the contact electrodes in a predetermined arrangement.

    摘要翻译： 接触器具有可在接触器的厚度方向上弹性变形的接触电极，使得接触器能够以适当的接触压力与半导体器件接触。 接触器位于半导体器件和测试板之间，以将半导体器件电连接到测试板。 多个接触电极中的每一个具有第一接触电极部分，第二接触电极部分和将第一接触电极部分电连接到第二接触电极部分的连接部分。 第一接触电极部分接触半导体器件的电极。 第二接触电极部分接触测试板的端子。 组合构件具有绝缘特性，并且以预定的布置保持每个接触电极的连接部分。

    Wafer-level package having test terminal
    49.
    发明申请
    Wafer-level package having test terminal 失效
    晶圆级封装有测试端子

    公开(公告)号：US20060202201A1

    公开(公告)日：2006-09-14

    申请号：US11433396

    申请日：2006-05-15

    申请人： Shigeyuki Maruyama

    发明人： Shigeyuki Maruyama

    IPC分类号： H01L23/58 ,  H01L23/48

    CPC分类号： H01L22/32 ,  G01R31/2831 ,  G01R31/2884 ,  H01L24/19 ,  H01L24/20 ,  H01L24/94 ,  H01L24/96 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/14

    摘要： A wafer-level package includes a semiconductor wafer having at least one semiconductor chip circuit forming region each including a semiconductor chip circuit each provided with test chip terminals and non test chip terminals, at least one external connection terminal, at least one redistribution trace provided on the semiconductor wafer, at least one testing member, and an insulating material. A first end of the redistribution trace is connected to one of the test chip terminals and a second end of said redistribution trace is extended out to a position offset from the chip terminals. The testing member is provided in an outer region of the semiconductor chip circuit forming region, and the second end of the redistribution trace is connected to the testing member.

    摘要翻译： 晶片级封装包括具有至少一个半导体芯片电路形成区域的半导体晶片，每个半导体芯片电路形成区域各自包括半导体芯片电路，每个半导体芯片电路分别具有测试芯片端子和非测试芯片端子，至少一个外部连接端子，至少一个再分布迹线 半导体晶片，至少一个测试构件和绝缘材料。 再分配迹线的第一端连接到测试芯片端子之一，并且所述再分布迹线的第二端延伸到与芯片端子偏移的位置。 测试构件设置在半导体芯片电路形成区域的外部区域中，再分布迹线的第二端连接到测试构件。