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116 条记录 (耗时 0.03 秒)

    CMOS circuit and semiconductor device
    44.
    发明授权
    CMOS circuit and semiconductor device 失效
    CMOS电路和半导体器件

    公开(公告)号：US08552796B2

    公开(公告)日：2013-10-08

    申请号：US13612620

    申请日：2012-09-12

    申请人： Kiyoo Itoh ,  Masanao Yamaoka

    发明人： Kiyoo Itoh ,  Masanao Yamaoka

    IPC分类号： G05F1/10

    CPC分类号： H03K19/00315 ,  H01L27/092

    摘要： A CMOS circuit and a semiconductor device having small leakage current and a low threshold voltage, and which is operated at high speed and with a small voltage amplitude, including an output stage circuit having MOSTs configured such that when their gates and sources are respectively set to an equal voltage, subthreshold leakage currents substantially flow between their drains and sources, and upon deactivation, a voltage is applied to the gate of each of the MOSTs to cause a reverse bias to be applied between the gate and source of the MOST. Upon activation of the circuit, the MOST is held in a reverse bias state or controlled to a forward bias state according to an input voltage.

    摘要翻译： 一种具有小的漏电流和低阈值电压的CMOS电路和半导体器件，其以高速和小的电压幅度工作，包括具有MOST的输出级电路，其配置使得当其栅极和源极分别设置为 相等的电压，亚阈值漏电流基本上在它们的漏极和源极之间流动，并且在去激活时，电压被施加到每个MOST的栅极，以引起在MOST的栅极和源极之间施加反向偏压。 在电路激活时，MOST保持在反向偏置状态或根据输入电压被控制到正向偏置状态。

    Semiconductor device with back-gate voltage control of a logic circuit
    45.
    发明授权
    Semiconductor device with back-gate voltage control of a logic circuit 失效
    具有逻辑电路的背栅极电压控制的半导体器件

    公开(公告)号：US08508283B2

    公开(公告)日：2013-08-13

    申请号：US13081145

    申请日：2011-04-06

    申请人： Takayuki Kawahara ,  Masanao Yamaoka

    发明人： Takayuki Kawahara ,  Masanao Yamaoka

    IPC分类号： H03K17/14 ,  G05F3/16

    CPC分类号： H01L27/1203 ,  H01L29/78645 ,  H01L29/78648

    摘要： Back-gate voltage control provides a high speed and low power consumption LSI operable in a wide temperature range in which a MOS transistor having back gates is used specifically according to operating characteristics of a circuit. In the LSI, an FD-SOI structure having an embedded oxide film layer is used and a lower semiconductor region of the embedded oxide film layer is used as a back gate. A voltage for back gates in logic circuits having a small load in logic circuit block is controlled in response to activation of the block from outside of the block. Transistors, in which the gate and the back gate are connected to each other, are used for the circuit generating the back gate driving signal, and logic circuits having a heavy load such as circuit block output section, and the back gates are directly controlled according to a gate input signal.

    摘要翻译： 背栅极电压控制提供了在具有根据电路的工作特性具体使用具有背栅的MOS晶体管的宽温度范围内可操作的高速度和低功耗的LSI。 在LSI中，使用具有嵌入的氧化膜层的FD-SOI结构，并且将埋入的氧化膜层的下半导体区域用作后栅。 在逻辑电路块中具有小负载的逻辑电路中的后门的电压响应于块外部的激活而被控制。 栅极和背栅彼此连接的晶体管用于产生背栅极驱动信号的电路，以及具有诸如电路块输出部分的重负载的逻辑电路，并且后门直接根据 到门输入信号。

    CMOS CIRCUIT AND SEMICONDUCTOR DEVICE
    46.
    发明申请
    CMOS CIRCUIT AND SEMICONDUCTOR DEVICE 失效
    CMOS电路和半导体器件

    公开(公告)号：US20130063200A1

    公开(公告)日：2013-03-14

    申请号：US13612620

    申请日：2012-09-12

    申请人： Kiyoo Itoh ,  Masanao Yamaoka

    发明人： Kiyoo Itoh ,  Masanao Yamaoka

    IPC分类号： H03K17/687

    CPC分类号： H03K19/00315 ,  H01L27/092

    摘要： A CMOS circuit and a semiconductor device having small leakage current and a low threshold voltage, and which is operated at high speed and with a small voltage amplitude, including an output stage circuit having MOSTs configured such that when their gates and sources are respectively set to an equal voltage, subthreshold leakage currents substantially flow between their drains and sources, and upon deactivation, a voltage is applied to the gate of each of the MOSTs to cause a reverse bias to be applied between the gate and source of the MOST. Upon activation of the circuit, the MOST is held in a reverse bias state or controlled to a forward bias state according to an input voltage.

    摘要翻译： 一种具有小的漏电流和低阈值电压的CMOS电路和半导体器件，其以高速和小电压幅度工作，包括具有MOST的输出级电路，其配置为使得当其栅极和源极分别设置为 相等的电压，亚阈值漏电流基本上在它们的漏极和源极之间流动，并且在去激活时，电压被施加到每个MOST的栅极，以引起在MOST的栅极和源极之间施加反向偏压。 在电路激活时，MOST根据输入电压保持在反向偏置状态或被控制到正向偏置状态。

    SEMICONDUCTOR DEVICE
    47.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20120307572A1

    公开(公告)日：2012-12-06

    申请号：US13587900

    申请日：2012-08-16

    申请人： Masanao Yamaoka ,  Kenichi Osada

    发明人： Masanao Yamaoka ,  Kenichi Osada

    IPC分类号： G11C7/06

    CPC分类号： G11C8/08 ,  G11C11/412

    摘要： The semiconductor device makes a comparison between a word-line timing signal for determining a word-line activation time and a reference signal, applies a back-gate bias for enlarging a read margin when the result of the comparison represents a low condition of the read margin, and applies a back-gate bias for enlarging a write margin when the comparison result represents a low condition of the write margin. The reference signal is selected depending on whether to compensate an operating margin fluctuating according to the word-line activation time (or word-line pulse width), or to compensate an operating margin fluctuating according to the process fluctuation (or variation in threshold voltage). By controlling the back-gate biases according to the word-line pulse width, an operating margin fluctuating according to the word-line pulse width, and an operating margin fluctuating owing to the variation in threshold voltage during its fabrication are improved.

    CMOS circuit and semiconductor device with multiple operation mode biasing
    48.
    发明授权
    CMOS circuit and semiconductor device with multiple operation mode biasing 失效
    CMOS电路和具有多种工作模式偏置的半导体器件

    公开(公告)号：US08294510B2

    公开(公告)日：2012-10-23

    申请号：US12521263

    申请日：2007-12-11

    申请人： Kiyoo Itoh ,  Masanao Yamaoka

    发明人： Kiyoo Itoh ,  Masanao Yamaoka

    IPC分类号： G05F1/10

    CPC分类号： H03K19/00315 ,  H01L27/092

    摘要： There is provided an output stage circuit including such MOSTs (M) that when their gates and sources are respectively set to an equal voltage, subthreshold leakage currents substantially flow between their drains and sources, wherein upon its deactivation, a voltage is applied to the gate of each of the MOSTs (M) in such a manner than a reverse bias is applied between the gate and source of the MOST (M). That is, when the MOST (M) is of a p channel type, a voltage higher than that of a p type source is applied to its gate. When the MOST (M) is of an n channel type, a voltage lower than that of an n type source is applied to its gate. Upon activation of the circuit, the MOST is held in a reverse bias state or controlled to a forward bias state according to an input voltage. A CMOS circuit and a semiconductor device can be realized each of which is small in leakage current even though its threshold voltage is low and which is operated at high speed and with a small voltage amplitude.

    摘要翻译： 提供了一种包括这样的MOST（M）的输出级电路，当它们的栅极和源极分别设置为相等的电压时，亚阈值漏电流基本上在它们的漏极和源极之间流动，其中当其去激活时，电压被施加到栅极 在MOST（M）的栅极和源极之间施加反向偏置的方式的每个MOST（M）。 也就是说，当MOST（M）是p沟道型时，其栅极施加比p型源高的电压。 当MOST（M）为n沟道型时，其栅极施加比n型源低的电压。 在电路激活时，MOST保持在反向偏置状态或根据输入电压被控制到正向偏置状态。 即使其阈值电压低，并且以高速度和小的电压幅度工作，也可以实现CMOS电路和半导体器件，每个CMOS电路和半导体器件的漏电流小。

    DETECTION SYSTEM, SEMICONDUCTOR DEVICE, AND DATA PROCESSING DEVICE
    49.
    发明申请
    DETECTION SYSTEM, SEMICONDUCTOR DEVICE, AND DATA PROCESSING DEVICE 失效
    检测系统，半导体器件和数据处理器件

    公开(公告)号：US20110115474A1

    公开(公告)日：2011-05-19

    申请号：US12917523

    申请日：2010-11-02

    申请人： Masanao Yamaoka ,  Kenichi Osada ,  Minoru Motoyoshi ,  Tetsuya Fukuoka

    发明人： Masanao Yamaoka ,  Kenichi Osada ,  Minoru Motoyoshi ,  Tetsuya Fukuoka

    IPC分类号： G01R5/14

    CPC分类号： G06F1/3203 ,  G06F1/206 ,  H01L21/67276 ,  Y02D10/16

    摘要： To provide an LSI having a low power mode that can prevent an apparatus on which the LSI is mounted from resulting in performance degradation, etc. even when its electric power is not reduced in the low power mode. Devised is a circuit that instructs an operation mode and detects whether the LSI operates as specified by the mode, and that measures a current at the time of the low power mode in a pseudo manner and, if despite having shifted to the low power mode, the current is not reduced actually, issues an alarm signal.

    摘要翻译： 为了提供具有低功率模式的LSI，即使在低功率模式下其电力没有降低的情况下，也可以防止LSI的装置在其中导致性能劣化等。 设计的是指示操作模式并且检测LSI是否以模式指定的方式操作的电路，并且以伪方式测量低功率模式时的电流，并且如果尽管已经转移到低功率模式， 电流实际上没有减少，发出报警信号。

    SEMICONDUCTOR MEMORY DEVICE
    50.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权
    半导体存储器件

    公开(公告)号：US20110012206A1

    公开(公告)日：2011-01-20

    申请号：US12891208

    申请日：2010-09-27

    申请人： Masanao Yamaoka ,  Kenichi Osada ,  Kazumasa Yanagisawa

    发明人： Masanao Yamaoka ,  Kenichi Osada ,  Kazumasa Yanagisawa

    IPC分类号： H01L27/088

    CPC分类号： G11C11/417 ,  G11C5/14 ,  G11C5/148

    摘要： When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.

    摘要翻译： 当降低构成晶体管的阈值电压以便在低电压下操作SRAM电路时，存在晶体管的漏电流增加的问题，结果是当SRAM电路不工作时的功耗 同时存储数据增加。 因此，提供了通过控制存储单元中的驱动器MOS晶体管的源极线ssl的电位来减小SRAM存储单元MC中的MOS晶体管的漏电流的技术。