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    Method to form an elevated S/D CMOS device by contacting S/D through the contact of oxide
    41.
    发明授权
    Method to form an elevated S/D CMOS device by contacting S/D through the contact of oxide 失效
    通过使氧化物的接触使S / D接触来形成升高的S / D CMOS器件的方法

    公开(公告)号：US06306714B1

    公开(公告)日：2001-10-23

    申请号：US09713802

    申请日：2000-11-16

    申请人： Yang Pan ,  James Yongmeng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan

    发明人： Yang Pan ,  James Yongmeng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan

    IPC分类号： H01L21336

    CPC分类号： H01L21/76877 ,  H01L29/41783 ,  H01L29/66492 ,  H01L29/66583 ,  H01L29/6659 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of fabrication of an elevated source/drain (S/D) for a MOS device. A first insulating layer having a gate opening and source/drain openings is formed over a substrate. We form a LDD resist mask having opening over the source/drain openings over the first insulating layer. Ions are implanted through the source/drain openings. A first dielectric layer is formed on the substrate in the gate opening and source/drain openings. A gate is formed in the gate opening and raised source/drain (S/D) blocks in the source/drain openings. We remove the spacer blocks to form spacer block openings. We form second LDD regions by implanting ions through the spacer block openings. We form second spacer blocks in the spacer block openings. Plug opening are formed through the raised source/drain (S/D) blocks. Contact plugs are formed in the form plug opening.

    摘要翻译： 制造用于MOS器件的升高的源极/漏极（S / D）的方法。 在衬底上形成具有栅极开口和源极/漏极开口的第一绝缘层。 我们形成了在第一绝缘层上的源/漏开口上方具有开口的LDD抗蚀剂掩模。 离子通过源极/漏极开口植入。 在栅极开口和源极/漏极开口中的基板上形成第一电介质层。 栅极形成在源极/漏极开口中的栅极开路和升高的源极/漏极（S / D）块中。 我们移除间隔块以形成间隔块开口。 我们通过将离子注入间隔块开口形成第二LDD区域。 我们在间隔块开口中形成第二间隔块。 插头开口通过凸起的源极/漏极（S / D）块形成。 接触塞以形式的塞子开口形成。

    Method to form an L-shaped silicon nitride sidewall spacer
    43.
    发明授权
    Method to form an L-shaped silicon nitride sidewall spacer 有权
    形成L形氮化硅侧壁间隔物的方法

    公开(公告)号：US06251764B1

    公开(公告)日：2001-06-26

    申请号：US09439368

    申请日：1999-11-15

    申请人： Yelehanka Ramachandramurthy Pradeep ,  Jie Yu ,  Guan Ping Wu

    发明人： Yelehanka Ramachandramurthy Pradeep ,  Jie Yu ,  Guan Ping Wu

    IPC分类号： H01L213205

    CPC分类号： H01L21/31116 ,  H01L21/3185 ,  H01L21/76832 ,  H01L21/76834 ,  H01L29/6659

    摘要： A new method of forming silicon nitride sidewall spacers has been achieved. This method is used to fabricate tapered, L-shaped spacer profiles using a two-step etching process that can be performed insitu. In accordance with the objects of this invention, a new method of forming silicon nitride sidewall spacers has been achieved. An isolation region is provided overlying a semiconductor substrate. Conductive traces are provided overlying the insulator layer. A liner oxide layer is deposited overlying the conductive traces and the insulator layer. A silicon nitride layer is deposited overlying the liner oxide layer. The silicon nitride layer is anisotropically etched down to reduce the vertical thickness of the silicon nitride layer while not exposing the underlying liner oxide layer. The silicon nitride layer is etched through to form silicon nitride sidewall spacers adjacent to the conductive traces. This etching through results in a tapered, L-shaped sidewall profile, and the integrated circuit device is completed.

    摘要翻译： 已经实现了形成氮化硅侧壁间隔物的新方法。 该方法用于使用可以在本发明中进行的两步蚀刻工艺来制造锥形的L形间隔件型材。 根据本发明的目的，已经实现了形成氮化硅侧壁间隔物的新方法。 设置在半导体衬底上的隔离区域。 导电迹线被覆盖在绝缘体层上。 衬底氧化层沉积在导电迹线和绝缘体层上。 沉积覆盖衬垫氧化物层的氮化硅层。 氮化硅层被各向异性地向下蚀刻以减小氮化硅层的垂直厚度，同时不暴露下面的衬里氧化物层。 蚀刻氮化硅层以形成邻近导电迹线的氮化硅侧壁间隔物。 该蚀刻导致锥形的L形侧壁轮廓，并且集成电路器件完成。

    Method of making direct contact on gate by using dielectric stop layer
    44.
    发明申请
    Method of making direct contact on gate by using dielectric stop layer 有权
    通过使用介电阻挡层在栅极上直接接触的方法

    公开(公告)号：US20050136573A1

    公开(公告)日：2005-06-23

    申请号：US11045958

    申请日：2005-01-28

    申请人： Purakh Rajverma ,  Sanford Chu ,  Lap Chan ,  Yelehanka Ramachandramurthy Pradeep ,  Kai Shao ,  Jia Zheng

    发明人： Purakh Rajverma ,  Sanford Chu ,  Lap Chan ,  Yelehanka Ramachandramurthy Pradeep ,  Kai Shao ,  Jia Zheng

    IPC分类号： H01L21/00 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/768 ,  H01L21/84 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L21/76802 ,  H01L21/76829

    摘要： A CMOS RF device and a method to fabricate said device with low gate contact resistance are described. Conventional MOS transistor is first formed with isolation regions, poly-silicon gate structure, sidewall spacers around poly gate, and implanted source/drain with lightly and heavily doped regions. A silicon dioxide layer such as TEOS is deposited, planarized with chemical mechanical polishing (CMP) to expose the gate and treated with dilute HF etchant to recess the silicon dioxide layer below the surface of the gate. Silicon nitride is then deposited and planarized with CMP and then etched except around the gates, using a oversize poly-silicon gate mask. Inter-level dielectric mask is then deposited, contact holes etched, and contact metal is deposited to form the transistor. During contact hole etch over poly-silicon gate, silicon nitride around the poly gate acts as an etch stop. Resulting structure with direct gate contact achieves significantly reduced gate resistance and thereby improved noise performance at high frequency operation, increased unit power gain frequency (fmax), and reduced gate delay.

    摘要翻译： 描述CMOS RF器件和制造具有低栅极接触电阻的所述器件的方法。 传统的MOS晶体管首先形成有隔离区域，多晶硅栅极结构，围绕多晶硅栅极的侧壁隔离物以及具有轻掺杂和重掺杂区域的注入源极/漏极。 沉积诸如TEOS的二氧化硅层，通过化学机械抛光（CMP）平坦化以暴露栅极，并用稀的HF蚀刻剂处理以使位于栅极表面下方的二氧化硅层凹陷。 然后将氮化硅沉积并用CMP平坦化，然后使用超大型多晶硅栅极掩模在栅极周围进行蚀刻。 然后沉积层间电介质掩模，蚀刻接触孔，并沉积接触金属以形成晶体管。 在多晶硅栅极的接触孔蚀刻期间，多晶硅周围的氮化硅作为蚀刻停止。 具有直接栅极接触的所得结构实现了显着降低的栅极电阻，从而改善了高频操作下的噪声性能，增加的单位功率增益频率（f max）和减小的栅极延迟。

    Method of forming an inductor with continuous metal deposition
    45.
    发明申请
    Method of forming an inductor with continuous metal deposition 审中-公开
    形成具有连续金属沉积的电感器的方法

    公开(公告)号：US20050124131A1

    公开(公告)日：2005-06-09

    申请号：US11034932

    申请日：2005-01-13

    申请人： Chit Hweing ,  Lap Chan ,  Purakh Verma ,  Yelehanka Ramachandramurthy Pradeep ,  Sanford Chu

    发明人： Chit Hweing ,  Lap Chan ,  Purakh Verma ,  Yelehanka Ramachandramurthy Pradeep ,  Sanford Chu

    IPC分类号： H01F17/00 ,  H01L21/02 ,  H01L23/522 ,  H01L21/20 ,  H01L29/00

    CPC分类号： H01L28/10 ,  H01F17/0006 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method is described to fabricate RF inductor devices on a silicon substrate. Low-k or other dielectric material is deposited and patterned to form inductor lower plate trenches. Trenches are lined with barrier film such as TaN, filled with copper, and excess metal planarized using chemical mechanical polishing (CMP). Second layer of a dielectric material is deposited and patterned to form via-hole/trenches. Via-hole/trench patterns are filled with barrier material, and the dielectric film in between the via-hole/trenches is etched to form a second set of trenches. These trenches are filled with copper and planarized. A third layer of a dielectric film is deposited and patterned to form via-hole/trenches. Via-hole/trenches are then filled with barrier material, and the dielectric film between via-hole/trench patterns etched to form a third set of trenches. These trenches are filled with copper metal and excess metal removed by CMP to form said RF inductor.

    摘要翻译： 描述了在硅衬底上制造RF电感器件的方法。 沉积低k或其他电介质材料并图案化以形成电感器下板沟槽。 沟槽衬有阻挡膜，如填充有铜的TaN和使用化学机械抛光（CMP）平坦化的多余金属。 介电材料的第二层被沉积并图案化以形成通孔/沟槽。 通孔/沟槽图案填充有阻挡材料，蚀刻通孔/沟槽之间的电介质膜以形成第二组沟槽。 这些沟槽用铜填充并平坦化。 电介质膜的第三层被沉积并图案化以形成通孔/沟槽。 然后用阻挡材料填充通孔/沟槽，蚀刻通孔/沟槽图案之间的电介质膜以形成第三组沟槽。 这些沟槽填充有铜金属，并通过CMP去除多余的金属以形成所述RF电感器。

    Method to form a self-aligned CMOS inverter using vertical device integration
    47.
    发明授权
    Method to form a self-aligned CMOS inverter using vertical device integration 失效
    使用垂直器件集成形成自对准CMOS反相器的方法

    公开(公告)号：US06461900B1

    公开(公告)日：2002-10-08

    申请号：US09981438

    申请日：2001-10-18

    申请人： Ravi Sundaresan ,  Yang Pan ,  James Lee Young Meng ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek

    发明人： Ravi Sundaresan ,  Yang Pan ,  James Lee Young Meng ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek

    IPC分类号： H01L2100

    CPC分类号： H01L21/84 ,  H01L21/823885 ,  H01L27/1203

    摘要： A method to form a closely-spaced, vertical NMOS and PMOS transistor pair in an integrated circuit device is achieved. A substrate comprises silicon implanted oxide (SIMOX) wherein an oxide layer is sandwiched between underlying and overlying silicon layers. Ions are selectively implanted into a first part of the overlying silicon layer to form a drain, channel region, and source for an NMOS transistor. The drain is formed directly overlying the oxide layer, the channel region is formed overlying the drain, and the source is formed overlying the channel region. Ions are selectively implanted into a second part of the overlying silicon layer to form a drain, channel region, and source for a PMOS transistor. The drain is formed directly overlying the oxide layer, the PMOS channel region is formed overlying the drain, and the source is formed overlying the channel region. The PMOS transistor drain is in contact with said NMOS transistor drain. A gate trench is etched through the NMOS and PMOS sources and channel regions. The gate trench terminates at the NMOS and PMOS drains and exposes the sidewalls of the NMOS and PMOS channel regions. A gate oxide layer is formed overlying the NMOS and PMOS channel regions and lining the gate trench. A polysilicon layer is deposited and etched back to form polysilicon sidewalls and to thereby form gates for the closely-spaced, vertical NMOS and PMOS transistor pair.

    摘要翻译： 实现了在集成电路器件中形成紧密间隔的垂直NMOS和PMOS晶体管对的方法。 衬底包括硅注入氧化物（SIMOX），其中氧化物层夹在下层和上层的硅层之间。 离子选择性地注入到上覆硅层的第一部分中以形成用于NMOS晶体管的漏极，沟道区和源极。 漏极直接形成在氧化层的上方，沟道区形成在漏极上方，源极形成在沟道区域的上方。 离子选择性地注入到上层硅层的第二部分中以形成用于PMOS晶体管的漏极，沟道区和源极。 漏极直接形成在氧化层的上方，PMOS沟道区形成在漏极上方，源极形成在沟道区域的上方。 PMOS晶体管漏极与所述NMOS晶体管漏极接触。 通过NMOS和PMOS源极和沟道区域蚀刻栅极沟槽。 栅极沟槽在NMOS和PMOS漏极处终止并暴露NMOS和PMOS沟道区的侧壁。 形成栅极氧化层，覆盖NMOS沟道区和PMOS沟道区，并衬在栅极沟槽。 沉积多晶硅层并回蚀刻以形成多晶硅侧壁，从而形成用于紧密间隔的垂直NMOS和PMOS晶体管对的栅极。

    Method to form an inverted staircase STI structure by etch-deposition-etch and selective epitaxial growth
    48.
    发明授权
    Method to form an inverted staircase STI structure by etch-deposition-etch and selective epitaxial growth 有权
    通过蚀刻沉积蚀刻和选择性外延生长形成倒置阶梯STI结构的方法

    公开(公告)号：US06461887B1

    公开(公告)日：2002-10-08

    申请号：US10038391

    申请日：2002-01-03

    申请人： Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung

    发明人： Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung

    IPC分类号： H01L2100

    CPC分类号： H01L21/76232

    摘要： A method of forming an inverted staircase shaped STI structure comprising the following steps. A semiconductor substrate having an overlying oxide layer is provided. The substrate having at least a pair of active areas defining an STI region therebetween. The oxide layer is etched a first time within the active areas to form first step trenches. The first step trenches having exposed sidewalls. Continuous side wall spacers are formed on said exposed first step trench sidewalls. The oxide layer is etched X+1 more successive times using the previously formed step side wall spacers as masks to form successive step trenches within the active areas. Each of the successive step trenches having exposed sidewalls and have side wall spacers successively formed on the successive step trench exposed sidewalls. The oxide layer is etched a final time using the previously formed step side wall spacers as masks to form final step trenches exposing the substrate within the active areas. The STI region comprising an inverted staircase shaped STI structure. The step side wall spacers are removed from the X+2 step trenches. A planarized active area silicon structure is formed within the X+2 and final step trenches.

    摘要翻译： 一种形成倒置阶梯状STI结构的方法，包括以下步骤。 提供具有上覆氧化物层的半导体衬底。 衬底具有至少一对在其间限定STI区的有源区。 首先在有源区内蚀刻氧化物层以形成第一级沟槽。 第一级沟槽具有暴露的侧壁。 连续的侧壁间隔件形成在所述暴露的第一阶梯沟槽侧壁上。 使用先前形成的步骤侧壁间隔物作为掩模，将氧化物层连续蚀刻X + 1次，以在有效区域内形成连续的台阶沟槽。 每个连续的台阶沟槽具有暴露的侧壁并且具有连续形成在连续的阶梯槽暴露侧壁上的侧壁间隔物。 使用先前形成的步骤侧壁间隔物作为掩模来最后蚀刻氧化物层，以形成在活性区域内暴露衬底的最终步骤沟槽。 STI区域包括倒置的阶梯状STI结构。 从X + 2台阶沟槽中移除台阶侧壁间隔物。 平面化的有源区硅结构形成在X + 2和最后阶梯沟内。

    Method to form a low parasitic capacitance pseudo-SOI CMOS device
    50.
    发明授权
    Method to form a low parasitic capacitance pseudo-SOI CMOS device 有权
    形成低寄生电容伪SOI CMOS器件的方法

    公开(公告)号：US06403485B1

    公开(公告)日：2002-06-11

    申请号：US09846177

    申请日：2001-05-02

    申请人： Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Lee Yong Meng ,  Ying Keung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan

    发明人： Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Lee Yong Meng ,  Ying Keung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan

    IPC分类号： H01L21302

    CPC分类号： H01L21/76895

    摘要： A method of forming a pseudo-SOI device having elevated source/drain (S/D) regions that can be extended for use as local interconnect is described. Shallow trench isolation (STI) regions separating adjacent active regions are provided within a semiconductor substrate. Polysilicon gate electrodes and associated SID extensions are fabricated in and on the substrate in the active regions wherein a hard mask layer overlies each of the gate electrodes. Dielectric spacers are formed on sidewalls of each of the gate electrodes. A polysilicon layer is deposited overlying the gate electrodes and the substrate. The polysilicon layer is polished back with a polish stop at the hard mask layer. The polysilicon layer is etched back whereby the polysilicon layer is recessed with respect to the gate electrodes. Thereafter, the polysilicon layer is etched away overlying the STI regions where a separation between adjacent active areas is desired. If a local interconnect is desired between adjacent active areas, the polysilicon layer is not etched away overlying the STI region separating those active areas. The hard mask layer is removed. Ions are implanted and driven in to form elevated S/D regions within the polysilicon layer adjacent to the gate electrodes to complete formation of transistors having elevated S/D regions.

    摘要翻译： 描述了一种形成具有可扩展的用于局部互连的源/漏（S / D）区域较高的伪SOI器件的方法。 分离相邻有源区的浅沟槽隔离（STI）区域设置在半导体衬底内。 多晶硅栅极电极和相关的SID延伸部分在其中硬掩模层覆盖每个栅极电极的有源区域内和衬底上制造。 在每个栅电极的侧壁上形成电介质间隔物。 沉积覆盖栅电极和衬底的多晶硅层。 在硬掩模层上用抛光光阑抛光多晶硅层。 多晶硅层被回蚀，由此多晶硅层相对于栅电极凹陷。 此后，将多晶硅层蚀刻掉，覆盖STI区域，其中期望相邻的有源区域之间的间隔。 如果在相邻的有源区域之间需要局部互连，则多晶硅层不会被覆盖在分离这些有源区域的STI区域之上。 去除硬掩模层。 离子被植入和驱动以在与栅电极相邻的多晶硅层内形成升高的S / D区，以完成具有升高的S / D区的晶体管的形成。