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282 records (took 0.031 seconds)

    Adjustable electrostatic discharge protection clamp
    43.
    发明授权
    Adjustable electrostatic discharge protection clamp 有权
    可调静电放电保护夹

    公开(公告)号：US06492859B2

    公开(公告)日：2002-12-10

    申请号：US09769084

    申请日：2001-01-24

    Applicant: Vladislav Vashchenko ,  Peter J. Hopper

    Inventor： Vladislav Vashchenko ,  Peter J. Hopper

    IPC: H03K508

    CPC classification number: H01L27/0259

    Abstract: In an ESD protection circuit for an analog bipolar circuit, the avalanche breakdown voltage of a reverse-coupled NPN BJT acting as an avalanche diode is adjusted to comply with breakdown voltage and latchup requirements by including a resistor between the base and collector of the BJT.

    Abstract translation: 在模拟双极电路的ESD保护电路中，通过在BJT的基极和集电极之间包括一个电阻，调节充当雪崩二极管的反向耦合NPN BJT的雪崩击穿电压，以符合击穿电压和闭锁要求。

    Interconnect exhibiting reduced parasitic capacitance variation
    44.
    发明授权
    Interconnect exhibiting reduced parasitic capacitance variation 有权

    公开(公告)号：US06414367B1

    公开(公告)日：2002-07-02

    申请号：US09429442

    申请日：1999-10-28

    Applicant: Peter J. Hopper

    Inventor： Peter J. Hopper

    IPC: H01L2352

    CPC classification number: H01L23/5283 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Adjacent metal lines of an interconnect metallization layer exhibit reduced variation in parasitic capacitance due to the presence of an intervening third metal line. The third metal line is electrically linked to one of the adjacent metal lines and is designed to project into the space between the adjacent metal lines, thereby elevating parasitic capacitance while reducing the range of variation of parasitic capacitance over a known range of critical dimensions. Thickness of the interlayer dielectric formed over the adjacent metal lines can be tailored to trigger penetration of the third metal line within a known range of critical dimensions.

    Process for forming physical gate length dependent implanted regions using dual polysilicon spacers
    45.
    发明授权
    Process for forming physical gate length dependent implanted regions using dual polysilicon spacers 有权
    使用双重多晶硅间隔物形成物理栅极长度相关注入区的工艺

    公开(公告)号：US5981346A

    公开(公告)日：1999-11-09

    申请号：US271062

    申请日：1999-03-17

    Applicant: Peter J. Hopper

    Inventor： Peter J. Hopper

    IPC: H01L21/28 ,  H01L21/336 ,  H01L29/423

    CPC classification number: H01L21/823412 ,  H01L21/28114 ,  H01L21/2815 ,  H01L27/088 ,  H01L29/42376 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66537 ,  H01L29/66545

    Abstract: Process for forming physical gate length dependent implanted regions in a semiconductor substrate. The process includes steps of first providing a semiconductor substrate (e.g. a silicon wafer) with a gate oxide layer on its surface, followed by the formation of a polysilicon gate layer on the gate oxide layer. An additional oxide layer is subsequently formed on the polysilicon gate layer. The resulting oxide/polysilicon stack is then patterned to form a patterned oxide/polysilicon stack layer that includes a patterned additional oxide layer and a patterned polysilicon gate layer. Next, a conformal silicon nitride layer is formed over the patterned oxide/polysilicon stack layer. The conformal silicon nitride layer is then etched (e.g. by an anisotropic etch) to form silicon nitride spacers on the sidewalls of the patterned oxide/polysilicon stack layer. After removal of the patterned additional oxide layer to leave the silicon nitride spacers extending above the patterned polysilicon gate layer, an additional polysilicon layer is deposited. The additional polysilicon layer is then etched (e.g. by an anisotropic plasma etch) to create dual (i.e. internal and external) polysilicon spacers on the sidewalls of the silicon nitride spacers. Next, dopant atoms (e.g. dopant atoms chosen to serve as a physical gate length dependent V.sub.T adjust implant) are implanted, through the patterned polysilicon gate layer, into the semiconductor substrate to create an implanted region while using the dual polysilicon spacers (the pitch and profile of their internal portions being dependent on the physical gate length) as an implant mask.

    Abstract translation: 用于在半导体衬底中形成物理栅长度的注入区的工艺。 该方法包括首先在其表面上提供半导体衬底（例如硅晶片）与栅极氧化物层，随后在栅极氧化物层上形成多晶硅栅极层的步骤。 随后在多晶硅栅极层上形成另外的氧化物层。 然后将所得的氧化物/多晶硅堆叠图案化以形成图案化的氧化物/多晶硅堆叠层，其包括图案化的附加氧化物层和图案化的多晶硅栅极层。 接下来，在图案化的氧化物/多晶硅堆叠层上形成共形氮化硅层。 然后蚀刻保形氮化硅层（例如通过各向异性蚀刻），以在图案化的氧化物/多晶硅堆叠层的侧壁上形成氮化硅间隔物。 在去除图案化的附加氧化物层以留下在图案化多晶硅栅极层上方延伸的氮化硅间隔物之后，沉积附加的多晶硅层。 然后蚀刻附加多晶硅层（例如通过各向异性等离子体蚀刻）以在氮化硅间隔物的侧壁上产生双重（即内部和外部）多晶硅间隔物。 接下来，掺杂剂原子（例如被选择用作物理栅极长度相关的VT调整注入的掺杂剂原子）通过图案化的多晶硅栅极层注入到半导体衬底中以产生注入区域，同时使用双重多晶硅间隔物（间距和 其内部部分的轮廓取决于物理栅极长度）作为植入物掩模。

    Semiconductor GMI magnetometer
    50.
    发明授权
    Semiconductor GMI magnetometer 有权
    半导体GMI磁力计

    公开(公告)号：US08680854B2

    公开(公告)日：2014-03-25

    申请号：US13309443

    申请日：2011-12-01

    Applicant: Terry Dyer ,  Anuraag Mohan ,  Peter J. Hopper

    Inventor： Terry Dyer ,  Anuraag Mohan ,  Peter J. Hopper

    IPC: G01R33/09 ,  G01R33/06 ,  G01R33/00

    CPC classification number: G01R33/063 ,  G01R33/0052 ,  H01L24/19

    Abstract: A giant magneto-impedance (GMI) magnetometer is formed in a semiconductor wafer fabrication sequence, which significantly reduces the size and cost of the GMI magnetometer. The semiconductor wafer fabrication sequence forms a magnetic conductor, a non-magnetic conductor that is wrapped around the magnetic conductor as a coil, and non-magnetic conductors that touch the opposite ends of the magnetic conductor.

    Abstract translation: 在半导体晶片制造序列中形成巨磁阻（GMI）磁力计，这显着地降低了GMI磁力计的尺寸和成本。 半导体晶片制造顺序形成磁导体，缠绕在作为线圈的磁性导体周围的非磁性导体以及接触磁导体相对端的非磁性导体。

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