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    FLEXIBLE METADATA ALLOCATION AND CACHING
    43.
    发明公开
    FLEXIBLE METADATA ALLOCATION AND CACHING 审中-公开

    公开(公告)号：US20240013819A1

    公开(公告)日：2024-01-11

    申请号：US18348716

    申请日：2023-07-07

    Applicant: Rambus Inc.

    Inventor： Taeksang Song ,  Steven Woo ,  Craig Hampel ,  John Eric Linstadt

    IPC: G11C7/10

    CPC classification number: G11C7/1084 ,  G11C7/1006

    Abstract: An apparatus and method for flexible metadata allocation and caching. In one embodiment of the method first and second requests are received from first and second applications, respectively, wherein the requests specify a reading of first and second data, respectively, from one or more memory devices. The circuit reads the first and second data in response to receiving the first and second requests. Receiving first and second metadata from the one or more memory devices in response to receiving the first and second requests. The first and second metadata correspond to the first and second data, respectively. The first and second data are equal in size, and the first and second metadata are unequal in size.

    Memory system with multiple open rows per bank
    44.
    发明授权
    Memory system with multiple open rows per bank 有权

    公开(公告)号：US11842761B2

    公开(公告)日：2023-12-12

    申请号：US17390370

    申请日：2021-07-30

    Applicant: Rambus Inc.

    Inventor： Thomas Vogelsang ,  John Eric Linstadt ,  Liji Gopalakrishnan

    IPC: G06F12/00 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4091 ,  G06F13/42

    CPC classification number: G11C11/4085 ,  G06F13/4282 ,  G11C11/4091 ,  G11C11/4094

    Abstract: A dynamic random access memory (DRAM) component (e.g., module or integrated circuit) can be configured to have multiple rows in the same bank open concurrently. The controller of the component divides the address space of the banks into segments based on row address ranges. These row address ranges do not necessarily correspond to row address ranges of the bank's subarrays (a.k.a. memory array tiles—MATs). When a command is sent to open a row, the controller marks a plurality of the segments as blocked. The controller thereby tracks address ranges in a bank where it will not open a second row unless and until the first row is closed. The memory component may store information about which, and how many, segments should be blocked in response to opening a row. This information may be read by the controller during initialization.

    Buffer circuit with adaptive repair capability
    46.
    发明授权
    Buffer circuit with adaptive repair capability 有权

    公开(公告)号：US11735287B2

    公开(公告)日：2023-08-22

    申请号：US18074188

    申请日：2022-12-02

    Applicant: Rambus Inc.

    Inventor： Scott C. Best ,  John Eric Linstadt ,  Paul William Roukema

    IPC: G11C29/00 ,  G11C29/44 ,  G11C5/04 ,  G11C11/401 ,  G11C29/02 ,  G11C29/52

    CPC classification number: G11C29/4401 ,  G11C5/04 ,  G11C11/401 ,  G11C29/022 ,  G11C29/52 ,  G11C29/76 ,  G11C29/783 ,  G11C29/88 ,  G11C2029/4402

    Abstract: A buffer circuit is disclosed. The buffer circuit includes a command address (C/A) interface to receive an incoming activate (ACT) command and an incoming column address strobe (CAS) command. A first match circuit includes first storage to store failure row address information associated with the memory, and first compare logic. The first compare logic is responsive to the ACT command, to compare incoming row address information to the stored failure row address information. A second match circuit includes second storage to store failure column address information associated with the memory, and second compare logic. The second compare logic is responsive to the CAS command, to compare the incoming column address information to the stored failure column address information. Gating logic maintains a state of a matching row address identified by the first compare logic during the comparison carried out by the second compare logic.

    Multi-Mode Memory Module and Memory Component
    48.
    发明申请
    Multi-Mode Memory Module and Memory Component 有权

    公开(公告)号：US20220382691A1

    公开(公告)日：2022-12-01

    申请号：US17830838

    申请日：2022-06-02

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth Lee Wright

    IPC: G06F13/16 ,  G06F13/28

    Abstract: A memory module comprises an address buffer circuit, a command/address channel, and a plurality of memory components controlled by the address buffer circuit via the command/address channel. At least one memory component comprises a plurality of data ports, a memory core to store data, and a data interface. The data interface is capable of transferring data between the memory core and the data ports. The data interface supports a first data width mode in which the data interface transfers data at a first bit width and a first burst length via the data ports. The data interface also supports a second data width mode in which the data interface transfers data at a second bit width and second burst length via the data ports. The first bit width is greater than the second bit width and the first burst length is shorter than the second burst length.

    Data-Buffer Component with Variable-Width Data Ranks and Configurable Data-Rank Timing
    49.
    发明申请
    Data-Buffer Component with Variable-Width Data Ranks and Configurable Data-Rank Timing 有权

    公开(公告)号：US20220245073A1

    公开(公告)日：2022-08-04

    申请号：US17677714

    申请日：2022-02-22

    Applicant: Rambus Inc.

    Inventor： Thomas J. Giovannini ,  John Eric Linstadt ,  Catherine Chen

    IPC: G06F13/16 ,  G06F13/42 ,  G06F13/40

    Abstract: A memory system supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules. Each memory module includes an address-buffer component, data-buffer components, and two sets of memory dies, each set termed a “timing rank,” that can be accessed independently. The one memory module is configured in a wide mode for the single-memory-module configuration, in which case both timing ranks work together, as a “package rank,” to communicate full-width data. Each of two memory modules are configured in a narrow mode for the dual-memory-module configuration, in which case one timing rank from each memory module communicates data in parallel to appear to the host as single package ranks. The data-buffer components support separate and configurable write and read delays for the different timing ranks on each module to provide read and write leveling within and between memory modules.

    Adjustable access energy and access latency memory system and devices
    50.
    发明授权
    Adjustable access energy and access latency memory system and devices 有权

    公开(公告)号：US11379136B2

    公开(公告)日：2022-07-05

    申请号：US17075357

    申请日：2020-10-20

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  John Eric Linstadt

    IPC: G06F3/06 ,  G11C11/4091 ,  G11C11/4076 ,  G11C7/06 ,  G11C7/22 ,  G11C7/18 ,  G11C11/4097

    Abstract: Same sized blocks of data corresponding to a single read/write command are stored in the same memory array of a memory device, but using different formats. A first one of these formats spreads the data in the block across a larger number of memory subarrays (a.k.a., memory array tiles—MATs) than a second format. In this manner, the data blocks stored in the first format can be accessed with lower latency than the blocks stored in the second format because more data can be read from the array simultaneously. In addition, since the data stored in the second format is stored in fewer subarrays, it takes less energy to read a block stored in the second format. Thus, a system may elect, on a data block by data block basis, whether to conserve power or improve speed.

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