公开(公告)号：US20100027790A1

公开(公告)日：2010-02-04

申请号：US11961848

申请日：2007-12-20

申请人： Balaji Vembu ,  Gary Graunke ,  Sathyamurthi Sadhasivan ,  Aditya Sreenivas

发明人： Balaji Vembu ,  Gary Graunke ,  Sathyamurthi Sadhasivan ,  Aditya Sreenivas

IPC分类号： H04N7/167 ,  H04L9/08

CPC分类号： G06F21/606

摘要： A method for delivering audio/video data through a hardware device using a software application comprises, at the hardware end, receiving an encrypted application key, an encrypted random session key, and encrypted audio/video data from the software. The hardware then decrypts the encrypted application key using a secret encryption key, decrypts the encrypted random session key using the application key, and decrypts the encrypted audio/video data using the random session key. The hardware may then deliver the unencrypted audio/video data by way of a display and speakers. The secret encryption key is securely embedded within the hardware device at an earlier point in time.

摘要翻译： 通过使用软件应用的硬件设备来传送音频/视频数据的方法包括在硬件端从软件接收加密的应用密钥，加密的随机会话密钥和加密的音频/视频数据。 然后硬件使用秘密加密密钥解密加密的应用密钥，使用应用密钥对加密的随机会话密钥进行解密，并使用随机会话密钥解密加密的音频/视频数据。 然后硬件可以通过显示器和扬声器传递未加密的音频/视频数据。 秘密加密密钥在较早的时间点安全地嵌入硬件设备内。

公开(公告)号：US07636441B2

公开(公告)日：2009-12-22

申请号：US10756444

申请日：2004-01-12

申请人： Balaji Vembu

发明人： Balaji Vembu

IPC分类号： H04L9/08 ,  H04L9/30

CPC分类号： G06F21/10 ,  G06F2221/0797 ,  H04L9/0841 ,  H04L9/0897 ,  H04L9/30 ,  H04L2209/60

摘要： Secure key exchange and protected content distribution between a first entity and a second entity in a processing system may be accomplished by generating, by the first entity, a first key, encrypting the first key with a public key of a third entity, and storing the encrypted first key in the third entity. The second entity generates a second key, encrypts the second key with the public key of the third entity, and stores the encrypted second key in the third entity. The third entity decrypts the encrypted first key and the encrypted second key, using the third entity's private key to obtain the first key and the second key, encrypts the first key using the second key, and stores the first key encrypted by the second key in the third entity. The second entity then obtains the first key encrypted by the second key, and decrypts, using the second key, the first key encrypted by the second key. The first key may then be used to encrypt content sent to from the second entity to the first entity.

摘要翻译： 在处理系统中的第一实体和第二实体之间的安全密钥交换和受保护的内容分发可以通过由第一实体生成第一密钥，用第三实体的公钥加密第一密钥来存储， 第三个实体加密的第一个密钥。 第二实体生成第二密钥，用第三实体的公开密钥对第二密钥进行加密，并将加密的第二密钥存储在第三实体中。 第三实体使用第三实体的私钥来解密加密的第一密钥和加密的第二密钥，以获得第一密钥和第二密钥，使用第二密钥加密第一密钥，并将由第二密钥加密的第一密钥存储在 第三个实体。 第二实体然后获得由第二密钥加密的第一密钥，并且使用第二密钥对由第二密钥加密的第一密钥进行解密。 然后可以将第一密钥用于加密从第二实体发送到第一实体的内容。

公开(公告)号：US20080001958A1

公开(公告)日：2008-01-03

申请号：US11480663

申请日：2006-06-30

申请人： Balaji Vembu ,  Aditya Navale ,  Wishwesh A. Gandhi

发明人： Balaji Vembu ,  Aditya Navale ,  Wishwesh A. Gandhi

IPC分类号： G09G5/39

CPC分类号： G06F12/1009 ,  G06F9/4401 ,  G06F9/4403 ,  G06F9/4411 ,  G06F9/45533 ,  G06F9/45558 ,  G06F12/109 ,  G06F13/28 ,  G06F2009/45579 ,  G06F2009/45583 ,  G06F2212/152 ,  G06T1/60

摘要： A method and apparatus for creating, updating, and using guest physical address (GPA) to host physical address (HPA) shadow translation tables for translating GPAs of graphics data direct memory access (DMA) requests of a computing environment implementing a virtual machine monitor to support virtual machines. The requests may be sent through a render or display path of the computing environment from one or more virtual machines, transparently with respect to the virtual machine monitor. The creating, updating, and using may be performed by a memory controller detecting entries sent to existing global and page directory tables, forking off shadow table entries from the detected entries, and translating GPAs to HPAs for the shadow table entries.

摘要翻译： 一种用于创建，更新和使用访客物理地址（GPA）以主机物理地址（HPA）影子转换表的方法和装置，用于将实现虚拟机监视器的计算环境的图形数据直接存储器访问（DMA）请求的GPA转换为 支持虚拟机。 可以通过虚拟机监视器透明地从一个或多个虚拟机通过计算环境的呈现或显示路径发送请求。 创建，更新和使用可以由存储器控制器执行，该存储器控制器检测发送到现有全局和页目录表的条目，从检测到的条目中分离影子表条目，以及将影子表条目的GPA转换为HPA。

公开(公告)号：US20180293701A1

公开(公告)日：2018-10-11

申请号：US15482680

申请日：2017-04-07

申请人： ABHISHEK R. APPU ,  Joydeep Ray ,  Altug Koker ,  Balaji Vembu ,  Pattabhiraman K ,  Matthew B. Callaway

发明人： ABHISHEK R. APPU ,  Joydeep Ray ,  Altug Koker ,  Balaji Vembu ,  Pattabhiraman K ,  Matthew B. Callaway

IPC分类号： G06T1/60 ,  G06T15/00 ,  G06F9/455 ,  G06F9/50 ,  G06F9/48

CPC分类号： G06T1/60 ,  G06F9/45558 ,  G06F9/4881 ,  G06F9/5038 ,  G06F2009/45579 ,  G06F2009/45591 ,  G06T15/005

摘要： An apparatus and method for dynamic provisioning, quality of service, and prioritization in a graphics processor. For example, one embodiment of an apparatus comprises a graphics processing unit (GPU) comprising a plurality of graphics processing resources; slice configuration hardware logic to logically subdivide the graphics processing resources into a plurality of slices; and slice allocation hardware logic to allocate a designated number of slices to each virtual machine (VM) of a plurality of VMs running in a virtualized execution environment, the slice allocation hardware logic to allocate different numbers of slices to different VMs based on graphics processing requirements and/or priorities of each of the VMs.

公开(公告)号：US20180285374A1

公开(公告)日：2018-10-04

申请号：US15477027

申请日：2017-04-01

申请人： Altug Koker ,  Prasoonkumar Surti ,  David Puffer ,  Subramaniam Maiyuran ,  Guei-Yuan Lueh ,  Abhishek R. Appu ,  Joydeep Ray ,  Balaji Vembu ,  Tomer Bar-On ,  Andrew T. Lauritzen ,  Hugues Labbe ,  John G. Gierach ,  Gabor Liktor

发明人： Altug Koker ,  Prasoonkumar Surti ,  David Puffer ,  Subramaniam Maiyuran ,  Guei-Yuan Lueh ,  Abhishek R. Appu ,  Joydeep Ray ,  Balaji Vembu ,  Tomer Bar-On ,  Andrew T. Lauritzen ,  Hugues Labbe ,  John G. Gierach ,  Gabor Liktor

IPC分类号： G06F17/30 ,  G06F9/38 ,  G06F9/30

摘要： In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180285158A1

公开(公告)日：2018-10-04

申请号：US15477026

申请日：2017-04-01

申请人： Abhishek R. Appu ,  Altug Koker ,  Balaji Vembu ,  Joydeep Ray ,  Kamal Sinha ,  Prasoonkumar Surti ,  Kiran C. Veernapu ,  Subramaniam Maiyuran ,  Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Guei-Yuan Lueh ,  David Puffer ,  Wenyin Fu ,  Nikos Kaburlasos ,  Bhushan M. Borole ,  Josh B. Mastronarde ,  Linda L. Hurd ,  Travis T. Schluessler ,  Tomasz Janczak ,  Abhishek Venkatesh ,  Kai Xiao ,  Slawomir Grajewski

发明人： Abhishek R. Appu ,  Altug Koker ,  Balaji Vembu ,  Joydeep Ray ,  Kamal Sinha ,  Prasoonkumar Surti ,  Kiran C. Veernapu ,  Subramaniam Maiyuran ,  Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Guei-Yuan Lueh ,  David Puffer ,  Wenyin Fu ,  Nikos Kaburlasos ,  Bhushan M. Borole ,  Josh B. Mastronarde ,  Linda L. Hurd ,  Travis T. Schluessler ,  Tomasz Janczak ,  Abhishek Venkatesh ,  Kai Xiao ,  Slawomir Grajewski

IPC分类号： G06F9/50 ,  G06T1/60 ,  G06T1/20 ,  G06T15/00 ,  G06F9/48 ,  G06F1/32

摘要： In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180191494A1

公开(公告)日：2018-07-05

申请号：US15394324

申请日：2016-12-29

申请人： Balaji Vembu ,  Vidhya Krishnan ,  Sandeep S. Sodhi ,  Scott Janus ,  Daniel Nemiroff

发明人： Balaji Vembu ,  Vidhya Krishnan ,  Sandeep S. Sodhi ,  Scott Janus ,  Daniel Nemiroff

IPC分类号： H04L9/08 ,  G06F21/57

CPC分类号： H04L9/14 ,  G06F21/74 ,  G06F21/75

摘要： An embodiment of a graphics apparatus may include a graphics processor including a kernel executor, and a security engine communicatively coupled to the graphics processor. The security engine may be configured to create a kernel security key, encrypt an executable kernel for the kernel executor in accordance with the kernel security key, and share the kernel security key with the graphics processor.

公开(公告)号：US09678795B2

公开(公告)日：2017-06-13

申请号：US13993089

申请日：2011-12-30

申请人： Altug Koker ,  Aditya Navale ,  Balaji Vembu ,  Murali Ramadoss

发明人： Altug Koker ,  Aditya Navale ,  Balaji Vembu ,  Murali Ramadoss

IPC分类号： G06F9/46 ,  G06F9/50 ,  G06F9/48 ,  G06F15/167 ,  G06F9/54 ,  G06F12/14

CPC分类号： G06F9/50 ,  G06F9/4812 ,  G06F9/545 ,  G06F12/1491 ,  G06F15/167

摘要： Transitions to ring 0, each time an application wants to use an adjunct processor, are avoided, saving central processor operating cycles and improving efficiency. Instead, initially each application is registered and setup to use adjunct processor resources in ring 3.

公开(公告)号：US20170091989A1

公开(公告)日：2017-03-30

申请号：US14865933

申请日：2015-09-25

申请人： Murali Ramadoss ,  Balaji Vembu ,  Hema C. Nalluri ,  Michael Apodaca ,  Jeffery S. Boles

发明人： Murali Ramadoss ,  Balaji Vembu ,  Hema C. Nalluri ,  Michael Apodaca ,  Jeffery S. Boles

IPC分类号： G06T15/80 ,  G06T1/20

CPC分类号： G06T15/80 ,  G06F9/48 ,  G06F9/4881 ,  G06T1/20

摘要： By scheduling/managing workload submission to a POSH pipe one can exploit parallelism with minimum impact to the software scheduler in some embodiments.

公开(公告)号：US09589159B2

公开(公告)日：2017-03-07

申请号：US12492513

申请日：2009-06-26

申请人： Balaji Vembu ,  Aditya Navale ,  Sathyamurthi Sadhasivan

发明人： Balaji Vembu ,  Aditya Navale ,  Sathyamurthi Sadhasivan

IPC分类号： G06F12/14 ,  G06F21/84 ,  G06F21/72 ,  H04L9/08

CPC分类号： G06F21/84 ,  G06F21/72 ,  H04L9/0841 ,  H04L2209/60

摘要： Two processing elements in a single platform may communicate securely to allow the platform to take advantage of the certain cryptographic functionality in one processing element. A first processing element, such as a bridge, may use its cryptographic functionality to request a key exchange with a second processing element, such as a graphics engine. Each processing element may include a global key which is common to the two processing elements and a unique key which is unique to each processing element. A key exchange may be established during the boot process the first time the system boots and, failing any hardware change, the same key may be used throughout the lifetime of the two processing elements. Once a secure channel is set up, any application wishing to authenticate a processing element without public-private cryptographic function may perform the authentication with the other processing element which shares a secure channel with the first processing element.

摘要翻译： 单个平台中的两个处理元件可以安全通信，以允许平台在一个处理元件中利用某些加密功能。 诸如桥接器的第一处理元件可以使用其加密功能来请求与诸如图形引擎的第二处理元件的密钥交换。 每个处理元件可以包括两个处理元件共有的全局密钥和每个处理元件唯一的唯一密钥。 在系统引导的第一次引导过程中可以建立密钥交换，并且在任何硬件改变失败的情况下，在两个处理元件的整个寿命期间可以使用相同的密钥。 一旦建立了安全通道，希望在没有公共 - 私人密码功能的情况下认证处理元件的任何应用程序可以与与第一处理元件共享安全通道的其他处理元件执行认证。