公开(公告)号：US09722062B2

公开(公告)日：2017-08-01

申请号：US14837053

申请日：2015-08-27

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo Nakayama ,  Hironobu Miyamoto ,  Ichiro Masumoto ,  Yasuhiro Okamoto ,  Shinichi Miyake ,  Hiroshi Kawaguchi

IPC: H01L29/06 ,  H01L29/778 ,  H01L29/207 ,  H01L29/66 ,  H01L29/20 ,  H01L29/423 ,  H01L29/40 ,  H01L29/417 ,  H01L29/10

CPC classification number: H01L29/7827 ,  H01L29/1066 ,  H01L29/1083 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7783

Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.

公开(公告)号：US20170103898A1

公开(公告)日：2017-04-13

申请号：US15385507

申请日：2016-12-20

Applicant: Renesas Electronics Corporation

Inventor： Takashi INOUE ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Hiroshi Kawaguchi ,  Toshiyuki Takewaki ,  Nobuhiro Nagura ,  Takayuki Nagai ,  Yoshinao Miura ,  Hironobu Miyamoto

IPC: H01L21/28 ,  H01L29/778 ,  H01L29/423 ,  H01L21/02 ,  H01L21/308

CPC classification number: H01L21/28264 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/308 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/452 ,  H01L29/513 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7787 ,  H01L29/7827

Abstract: A method of manufacturing a semiconductor device includes forming a first nitride semiconductor layer, forming thereover a second nitride semiconductor layer having a band gap wider than that of the first nitride semiconductor layer, and thereby forming a stacked body, etching the stacked body with a first film placed over the stacked body and including a first opening portion as a mask to form a trench penetrating through the second nitride semiconductor layer and reaching an inside of the first nitride semiconductor layer, causing an end portion of the first film to retreat from an end portion of the trench, forming a second film over the first film including the inside of the trench, and forming a gate electrode over the second film.

公开(公告)号：US09559183B2

公开(公告)日：2017-01-31

申请号：US14271277

申请日：2014-05-06

Applicant: Renesas Electronics Corporation

Inventor： Takashi Inoue ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Hiroshi Kawaguchi ,  Toshiyuki Takewaki ,  Nobuhiro Nagura ,  Takayuki Nagai ,  Yoshinao Miura ,  Hironobu Miyamoto

IPC: H01L29/778 ,  H01L29/201 ,  H01L29/205 ,  H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/40 ,  H01L21/336 ,  H01L29/45 ,  H01L29/20

CPC classification number: H01L21/28264 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/308 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/452 ,  H01L29/513 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7787 ,  H01L29/7827

Abstract: To provide a semiconductor device having improved characteristics. The semiconductor device has a substrate and thereon a buffer layer, a channel layer, a barrier layer, a trench penetrating therethrough and reaching the inside of the channel layer, a gate electrode placed in the trench via a gate insulating film, and drain and source electrodes on the barrier layer on both sides of the gate electrode. The gate insulating film has a first portion made of a first insulating film and extending from the end portion of the trench to the side of the drain electrode and a second portion made of first and second insulating films and placed on the side of the drain electrode relative to the first portion. The on resistance can be reduced by decreasing the thickness of the first portion at the end portion of the trench on the side of the drain electrode.

Abstract translation: 提供具有改进特性的半导体器件。 半导体器件具有衬底，其上具有缓冲层，沟道层，阻挡层，穿透其中并到达沟道层内部的沟槽，通过栅极绝缘膜放置在沟槽中的栅电极，以及漏极和源极 位于栅电极两侧的阻挡层上的电极。 栅极绝缘膜具有由第一绝缘膜形成并从沟槽的端部延伸至漏极侧的第一部分和由第一绝缘膜和第二绝缘膜构成的第二部分，并且设置在漏电极侧 相对于第一部分。 可以通过减小在漏电极侧的沟槽的端部处的第一部分的厚度来减小导通电阻。

公开(公告)号：US09530879B2

公开(公告)日：2016-12-27

申请号：US14947172

申请日：2015-11-20

Applicant: Renesas Electronics Corporation

Inventor： Yasuhiro Okamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota

IPC: H01L29/00 ,  H01L29/778 ,  H01L29/205 ,  H01L29/66 ,  H01L29/20 ,  H01L29/423 ,  H01L29/201 ,  H01L29/51

CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786

Abstract: A semiconductor device including a field effect transistor including a substrate, a lower barrier layer provided on the substrate, a channel layer provided on the lower barrier layer, an electron supplying layer provided on the channel layer, a source electrode and a drain electrode provided on the electron layer, and a gate electrode provided between the source electrode and the drain electrode. The lower barrier layer includes a composition of In1-zAlzN (0≦z≦1). The channel layer includes a composition of AlxGa1-xN (0≦x≦1). A recess is provided in a region between the source electrode and the drain electrode, wherein the recess goes through the electron supplying layer to a depth that exposes the channel layer, and the gate electrode is disposed on a gate insulating film that covers a bottom surface and an inner wall surface of the recess.

Abstract translation: 一种包括场效应晶体管的半导体器件，包括衬底，设置在衬底上的下阻挡层，设置在下阻挡层上的沟道层，设置在沟道层上的电子供给层，设置在沟道层上的源电极和漏电极 电子层和设置在源电极和漏电极之间的栅电极。 下阻挡层包括In1-zAlzN（0≤z≤1）的组成。 沟道层包括Al x Ga 1-x N（0≤x≤1）的组成。 在源电极和漏电极之间的区域设置有凹部，其中，凹部穿过电子供给层到达暴露沟道层的深度，并且栅电极设置在覆盖底面的栅极绝缘膜上 和凹部的内壁表面。

公开(公告)号：US20160133715A1

公开(公告)日：2016-05-12

申请号：US14982541

申请日：2015-12-29

Applicant: Renesas Electronics Corporation

Inventor： Yasuhiro Okamoto ,  Takashi Inoue ,  Tatsuo Nakayama ,  Ryohei Nega ,  Masaaki Kanazawa ,  Hironobu Miyamoto

IPC: H01L29/45 ,  H01L29/205 ,  H01L29/778 ,  H01L29/20

CPC classification number: H01L29/452 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The reliability of a field effect transistor made of a nitride semiconductor material is improved. An ohmic electrode includes a plurality of unit electrodes isolated to be separated from each other. With this configuration, an on-state current can be prevented from flowing in the unit electrodes in a y-axial direction (negative direction). Further, in the respective unit electrodes, a current density of the on-state current flowing in the y-axial direction (negative direction) can be prevented from increasing. As a result, an electromigration resistance of the ohmic electrode can be improved.

Abstract translation: 提高了由氮化物半导体材料制成的场效应晶体管的可靠性。 欧姆电极包括被隔离以彼此分离的多个单元电极。 由此，能够防止在y轴方向（负方向）在单位电极中流通导通电流。 此外，在各单元电极中，可以防止沿y轴方向（负方向）流动的通态电流的电流密度增加。 结果，可以提高欧姆电极的电迁移电阻。

公开(公告)号：US09337325B2

公开(公告)日：2016-05-10

申请号：US14229645

申请日：2014-03-28

Applicant: Renesas Electronics Corporation

Inventor： Takashi Inoue ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Hironobu Miyamoto

IPC: H01L21/336 ,  H01L29/778 ,  H01L21/02 ,  H01L29/205 ,  H01L29/66 ,  H01L29/423 ,  H01L29/43 ,  H01L29/51 ,  H01L29/20

CPC classification number: H01L29/778 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/432 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783

Abstract: A method for manufacturing a semiconductor device includes forming a buffer layer made of a nitride semiconductor, forming a channel layer made of a nitride semiconductor over the buffer layer, forming a barrier layer made of a nitride semiconductor over the channel layer, forming a cap layer made of a nitride semiconductor over the barrier layer, forming a gate insulating film so as to in contact with the cap layer; and forming a gate electrode over the gate insulating film, wherein compression strains are generated at an interface between the cap layer and the barrier layer and an interface between the channel layer and the buffer layer and a tensile strain is generated at an interface between the barrier layer and the channel layer by controlling compositions of the cap layer, the barrier layer, the channel layer, and the buffer layer.

Abstract translation: 一种半导体器件的制造方法，包括：形成由氮化物半导体构成的缓冲层，在所述缓冲层上形成由氮化物半导体构成的沟道层，在所述沟道层上形成由氮化物半导体构成的阻挡层，形成覆盖层 由阻挡层上的氮化物半导体形成，形成栅极绝缘膜以与盖层接触; 以及在所述栅极绝缘膜上形成栅电极，其中在所述覆盖层和所述阻挡层之间的界面处产生压缩应变，以及在所述沟道层和所述缓冲层之间的界面处产生压应变，并且在所述栅极之间的界面处产生拉伸应变 层和沟道层，通过控制盖层，阻挡层，沟道层和缓冲层的组成。

公开(公告)号：US20150048419A1

公开(公告)日：2015-02-19

申请号：US14332954

申请日：2014-07-16

Applicant: Renesas Electronics Corporation

Inventor： Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Takashi Inoue

IPC: H01L29/205 ,  H01L29/778 ,  H01L29/20 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7787 ,  H01L21/28264 ,  H01L29/0692 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7789

Abstract: A semiconductor device has a channel layer formed above a substrate, a barrier layer formed over the channel layer and having a band gap larger than that of the channel layer, a trench passing through the barrier layer as far as a midway of the channel layer, and a gate electrode disposed byway of a gate insulation film in the inside of the trench. Then, the end of the bottom of the trench is in a rounded shape and the gate insulation film in contact with the end of the bottom of the trench is in a rounded shape. By providing the end of the bottom of the trench with a roundness as described above, a thickness of the gate insulation film situated between the end of the bottom of the gate electrode and the end of the bottom of the trench can be decreased. Thus, the channel is formed also at the end of the bottom of the trench to reduce the resistance of the channel.

Abstract translation: 半导体器件具有在衬底上形成的沟道层，形成在沟道层上方并且具有比沟道层大的带隙的势垒层的沟道层，通过阻挡层的沟道至沟道层的中间， 以及在沟槽内部通过栅极绝缘膜设置的栅电极。 然后，沟槽底部的端部为圆形，并且与沟槽底部的端部接触的栅极绝缘膜为圆形。 通过如上所述地提供具有圆度的沟槽底部的端部，可以减小位于栅电极的底部端部和沟槽底部端部之间的栅极绝缘膜的厚度。 因此，沟道也形成在沟槽底部的端部以减小沟道的电阻。

公开(公告)号：US20140367743A1

公开(公告)日：2014-12-18

申请号：US14470403

申请日：2014-08-27

Applicant: Renesas Electronics Corporation

Inventor： Takashi Inoue ,  Tatsuo Nakayama ,  Yuji Ando ,  Yasuhiro Murase ,  Kazuki Ota ,  Hironobu Miyamoto ,  Katsumi Yamanoguchi ,  Naotaka Kuroda ,  Akio Wakejima ,  Yasuhiro Okamoto

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/06 ,  H01L29/20

CPC classification number: H01L29/7783 ,  H01L29/0607 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/7787

Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer). To gate length Lg of a FET to be prepared, a sum a of layer thicknesses of an electron supply layer and a channel layer is selected so as to fulfill Lg/a≧5, and in such a case, the layer thickness of the channel layer is selected in a range of not exceeding 5 times (about 500 Å) as long as a de Broglie wavelength of two-dimensional electron gas accumulated in the channel layer in room temperature.

Abstract translation: 在III族氮化物型场效应晶体管中，本发明通过缓冲层中的残留载流子的传导来减少漏电流成分，并且可以实现击穿电压的提高，并且提高了载流子限制效应（载流子限制） 提高夹断特性的通道（抑制短路效应）。 例如，当将本发明应用于GaN型场效应晶体管时，除了沟道层的GaN之外，使用其中铝组成逐渐或逐步朝向顶部的组分调制（组成梯度）AlGaN层用作 缓冲层（杂质缓冲液）。 对于要制备的FET的栅极长度Lg，选择电子供给层和沟道层的层厚度的和a以满足Lg /a≥5，并且在这种情况下，沟道的层厚度 只要在室温下积聚在通道层中的二维电子气的德布罗意波长，不超过5倍（约500）的范围内选择层。