公开(公告)号：US20180151223A1

公开(公告)日：2018-05-31

申请号：US15639540

申请日：2017-06-30

Applicant: STMicroelectronics S.r.l.

Inventor： Cesare Torti ,  Fabio Enrico Carlo Disegni ,  Davide Manfre' ,  Massimo Fidone

IPC: G11C13/00 ,  H01L27/24

CPC classification number: G11C13/0028 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0069 ,  H01L27/2436 ,  H01L29/7841 ,  H01L45/06

Abstract: A memory device includes an array of phase-change memory cells and a word line. The memory device includes a control circuit, a first pull-up MOSFET and a second pull-up MOSFET connected in series between a first power-supply node set at a first supply voltage and the word line, a first pull-down MOSFET and a second pull-down MOSFET connected in series between the word line and a second power-supply node set at a reference potential, and a biasing MOSFET connected between the word line and a third power-supply node set at a second supply voltage higher than the first supply voltage. The first and second pull-up MOSFETs and the first and second pull-down MOSFETs have breakdown voltages lower than the breakdown voltage of the biasing MOSFET.

公开(公告)号：US11915008B2

公开(公告)日：2024-02-27

申请号：US17654537

申请日：2022-03-11

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Application GMBH

Inventor： Roberto Colombo ,  Nicolas Bernard Rene Grossier ,  Fabio Enrico Carlo Disegni

IPC: G06F9/44 ,  G06F9/4401 ,  G06F9/30

CPC classification number: G06F9/4403 ,  G06F9/30101

Abstract: In an embodiment, a hardware configuration circuit reads and decodes an encoded life-cycle data and provides the decoded life-cycle data to a hardware circuit. A reset circuit monitors an external reset signal received via a reset terminal and, in response to determining that the external reset signal has a first logic level, executes a reset, a configuration, and a wait phase. The reset circuit waits until the external reset signal has a second logic level. A communication interface is activated during the wait phase and configured to receive a request. A hardware verification circuit generates a life-cycle advancement request signal when the request includes a given reference password and a reset circuit is in the wait phase. A write circuit writes a bit of the encoded life-cycle data stored in a non-volatile memory when the life-cycle advancement request signal is set, advancing the life-cycle to a given predetermined life-cycle stage.

公开(公告)号：US20220164131A1

公开(公告)日：2022-05-26

申请号：US17667087

申请日：2022-02-08

Applicant: STMicroelectronics S.r.l.

Inventor： Fabio Enrico Carlo Disegni

IPC: G06F3/06

Abstract: A method for operating a differential memory includes: operating a main memory module differentially while executing a first program; copying first logic data from a first submodule of the main memory module to an auxiliary memory module; storing third logic data associated with a second program in a second submodule of the main memory module by overwriting second logic data associated with the first program, while maintaining the first logic data contained in the first submodule of the main memory module unaltered, where the second logic data are complementary to the first logic data; when a request for reading the first logic data is received during the storing of the third logic data in the second submodule of the main memory module, reading the first logic data from the auxiliary memory module; and executing the first or second programs by operating the main memory module in single-ended mode.

公开(公告)号：US11322201B2

公开(公告)日：2022-05-03

申请号：US17159381

申请日：2021-01-27

Applicant: STMicroelectronics S.r.l.

Inventor： Maurizio Francesco Perroni ,  Fabio Enrico Carlo Disegni ,  Michele La Placa ,  Cesare Torti

IPC: G11C13/00

Abstract: An embodiment voltage generation circuit, for a memory having a memory array with a plurality of memory cells coupled to respective wordlines and local bit-lines, each having a storage element and selector element, a bipolar transistor being coupled to the storage element for selective flow of a cell current during reading or verifying operations, and a base terminal of the selector element being coupled to a respective wordline; associated to each bit-line is a biasing transistor having a control terminal, and the circuit generates a cascode voltage for this control terminal; a driver stage is coupled to one end of each wordline. The circuit generates the cascode voltage based on a reference voltage, which is a function of the emulation of a voltage drop on the driver stage, on the wordline, and on the memory cell as a result of a current associated to the corresponding selector element.

公开(公告)号：US20210383865A1

公开(公告)日：2021-12-09

申请号：US17410141

申请日：2021-08-24

Applicant: STMicroelectronics S.r.l.

Inventor： Michele La Placa ,  Fabio Enrico Carlo Disegni ,  Federico Goller

IPC: G11C13/00 ,  H01L45/00

Abstract: In an embodiment, a method includes receiving, between a positive input terminal and a negative input terminal, a supply voltage, receiving a data signal, generating, by a voltage generator in a branch of a plurality of branches, a branch current as a function of a respective driving signal and of a regulated voltage, each branch connected between the positive input terminal and the negative input terminal, selectively activating the voltage generator as a function of a respective enabling signal and providing, between a positive output terminal and a negative output terminal, the regulated voltage to one or more driving circuits.

公开(公告)号：US20210366554A1

公开(公告)日：2021-11-25

申请号：US17306266

申请日：2021-05-03

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics International N.V.

Inventor： Fabio Enrico Carlo Disegni ,  Laura Capecchi ,  Marcella Carissimi ,  Vikas Rana ,  Cesare Torti

IPC: G11C16/10 ,  G11C16/28 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  G11C16/32 ,  G11C7/06

Abstract: An embodiment non-volatile memory device includes an array of memory cells in rows and columns; a plurality of local bitlines, the memory cells of each column being coupled to a corresponding local bitline; a plurality of main bitlines, each main bitline being coupleable to a corresponding subset of local bitlines; a plurality of program driver circuits, each having a corresponding output node and injecting a programming current in the corresponding output node, each output node coupleable to a corresponding subset of main bitlines. Each program driver circuit further includes a corresponding limiter circuit that is electrically coupled, for each main bitline of the corresponding subset, to a corresponding sense node whose voltage depends, during writing, on the voltage on the corresponding main bitline. Each limiter circuit turns off the corresponding programming current, in case the voltage on any of the corresponding sense nodes overcomes a reference voltage.

公开(公告)号：US20210166745A1

公开(公告)日：2021-06-03

申请号：US17088060

申请日：2020-11-03

Applicant: STMicroelectronics S.r.l.

Inventor： Fabio Enrico Carlo Disegni ,  Maurizio Francesco Perroni ,  Cesare Torti ,  Guiseppe Scardino

IPC: G11C8/10 ,  G11C8/08

Abstract: A non-volatile memory device including an array of memory cells coupled to word lines and a row decoder, which includes a first and a second pull-down stage, which are arranged on opposite sides of the array, and include, respectively, for each word line, a corresponding first pull-down switching circuit and a corresponding second pull-down switching circuit, which are coupled to a first point and a second point, respectively, of the first word line. The row decoder moreover comprises a pull-up stage, which includes, for each word line, a corresponding pull-up switching circuit, which can be electronically controlled in order to: couple the first point to a supply node in the step of deselection of the word line; and decouple the first point from the supply node in the step of selection of the word line.

公开(公告)号：US20210020237A1

公开(公告)日：2021-01-21

申请号：US16931335

申请日：2020-07-16

Applicant: STMicroelectronics S.r.l.

Inventor： Marcella Carissimi ,  Laura Capecchi ,  Marco Pasotti ,  Fabio Enrico Carlo Disegni

IPC: G11C13/00

Abstract: A sense amplifier and a method for accessing a memory device are disclosed. In an embodiment a sense amplifier for a memory device includes a first input node selectively coupled to a first memory cell through a first local bitline and a first main bitline, a second input node selectively coupled through a second local bitline and a second main bitline to a second memory cell or to a reference generator configured to generate a reference current, a first current generator controllable so as to inject a first variable current into the first input node, a second current generator controllable so as to inject a second variable current into the second input node, a first branch coupled to the first input node and comprising a first switch circuit, a first sense transistor and a first forcing transistor and a second branch coupled to the second input node and including a second switch circuit, a second sense transistor and a second forcing transistor.

公开(公告)号：US10861543B2

公开(公告)日：2020-12-08

申请号：US16804698

申请日：2020-02-28

Applicant: STMicroelectronics S.r.l.

Inventor： Fabio Enrico Carlo Disegni ,  Cesare Torti ,  Davide Manfré

IPC: G11C11/00 ,  G11C13/00 ,  G11C7/18 ,  G06F13/16 ,  G06F13/40

Abstract: In one embodiment, a memory device includes a first sense amplifier, a second sense amplifier, a first lower switch arranged between a first lower main bit line and a first input of the first sense amplifier, a second lower switch arranged between the first lower main bit line and a first input of the second sense amplifier, a first upper switch arranged between a first upper main bit line and the first input of the first sense amplifier, a second upper switch arranged between the first upper main bit line and the first input of the second sense amplifier, a third lower switch arranged between a second lower main bit line to a second input of the first sense amplifier, and a third upper switch arranged between a second upper main bit line to a second input of the second sense amplifier.

公开(公告)号：US10658032B2

公开(公告)日：2020-05-19

申请号：US16155659

申请日：2018-10-09

Applicant: STMicroelectronics S.r.l.

Inventor： Cesare Torti ,  Fabio Enrico Carlo Disegni ,  Davide Manfré ,  Massimo Fidone

IPC: G11C13/00 ,  G11C8/08 ,  H01L27/24 ,  G11C5/14 ,  H01L29/78 ,  H01L45/00

Abstract: A memory device includes an array of phase-change memory cells and a word line. The memory device includes a control circuit, a first pull-up MOSFET and a second pull-up MOSFET connected in series between a first power-supply node set at a first supply voltage and the word line, a first pull-down MOSFET and a second pull-down MOSFET connected in series between the word line and a second power-supply node set at a reference potential, and a biasing MOSFET connected between the word line and a third power-supply node set at a second supply voltage higher than the first supply voltage. The first and second pull-up MOSFETs and the first and second pull-down MOSFETs have breakdown voltages lower than the breakdown voltage of the biasing MOSFET.