公开(公告)号：US20220139904A1

公开(公告)日：2022-05-05

申请号：US17325821

申请日：2021-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taemin Ok ,  Inmo Kim ,  Sujeong Kim ,  Daeseok Byeon

IPC: H01L27/02 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/06 ,  H01L23/538

Abstract: An integrated circuit device includes a semiconductor substrate having components of a peripheral circuit structure formed in and on a surface of the semiconductor substrate. The peripheral circuit structure comprising a plurality of protective antenna diodes therein. A memory cell array structure is provided on at least a portion of the peripheral circuit structure. A charge accumulating conductive plate is provided, which extends between the peripheral circuit structure and the memory cell array structure. The conductive plate is electrically connected to current carrying terminals of the antenna diodes within the peripheral circuit structure. The conductive plate may have a generally rectangular planar shape with four corners, and the antenna diodes may be arranged into four groups, which extend between respective corners of the conductive plate and the semiconductor substrate.

公开(公告)号：US11270759B2

公开(公告)日：2022-03-08

申请号：US17006990

申请日：2020-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chanho Kim ,  Daeseok Byeon ,  Hyunsurk Ryu

IPC: G11C5/06 ,  G11C11/4094 ,  G11C16/08 ,  G11C11/4093 ,  G11C11/408 ,  G06N3/063 ,  G11C16/04

Abstract: A flash memory device includes: first pads; second pads; third pads; a memory cell region including first metal pads and a memory cell array; and a peripheral circuit region including a second metal pads and vertically connected to the memory cell region by the first metal pads and the second metal pads directly. The peripheral circuit region includes a row decoder block; a buffer block storing a command and an address received from an external semiconductor chip through the first pads; a page buffer block connected to the memory cell array through bit lines, connected to the third pads through data lines, and exchanging data signals with the external semiconductor chip through the data lines and the third pads; and a control logic block receiving control signals from the external semiconductor chip through the second pads, and controlling the row decoder block and the page buffer block.

公开(公告)号：US11157425B2

公开(公告)日：2021-10-26

申请号：US16853807

申请日：2020-04-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngmin Jo ,  Daeseok Byeon ,  Tongsung Kim

IPC: G06F13/16 ,  G06N3/04 ,  H01L25/065 ,  H01L25/18

Abstract: A memory device provides a first memory area and a second memory area. A smart buffer includes; a priority setting unit receiving sensing data and a corresponding weight, determining a priority of the sensing data based on the corresponding weight, and classifying the sensing data as first priority sensing data or second priority sensing data based on the priority, and a channel controller allocating a channel to a first channel group, allocating another channel to a second channel group, assigning the first channel group to process the first priority sensing data in relation to the first memory area, and assigning the second channel group to process the second priority sensing data in relation to the second memory area.

公开(公告)号：US20210149598A1

公开(公告)日：2021-05-20

申请号：US16918310

申请日：2020-07-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghyuk Choi ,  Jaeduk Yu ,  Sangwan Nam ,  Sangwon Park ,  Daeseok Byeon ,  Bongsoon Lim

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24

Abstract: A nonvolatile memory device includes a first semiconductor layer including an upper substrate in which word-lines extending in a first direction and bit-lines extending in a second direction are disposed and a memory cell array, a second semiconductor layer, a control circuit, and a pad region. The memory cell array includes a vertical structure on the upper substrate, and the vertical structure includes memory blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The vertical structure includes via areas in which one or more through-hole vias are provided, and the via areas are spaced apart in the second direction. The memory cell array includes mats corresponding to different bit-lines of the bit-lines. At least two of the mats include a different number of the via areas according to a distance from the pad region in the first direction.

公开(公告)号：US20210065751A1

公开(公告)日：2021-03-04

申请号：US16816476

申请日：2020-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jooyong Park ,  Chanho Kim ,  Daeseok Byeon

IPC: G11C5/06 ,  G11C7/18 ,  G11C5/04

Abstract: A memory device includes a first semiconductor chip including a memory cell array disposed on a first substrate, and a first bonding metal on a first uppermost metal layer of the first semiconductor chip, and a second semiconductor chip including circuit devices disposed on a second substrate and a second bonding metal on a second uppermost metal layer of the second semiconductor chip, the circuit devices providing a peripheral circuit operating the memory cell array. The first and second semiconductor chips are electrically connected to each other by the first bonding metal and the second bonding metal in a bonding area. A routing wire electrically connected to the peripheral circuit is disposed in one or both of the first and second uppermost metal layers and is disposed in a non-bonding area in which the first and second semiconductor chips are not electrically connected to each other.

公开(公告)号：US09627084B2

公开(公告)日：2017-04-18

申请号：US15085498

申请日：2016-03-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donghun Kwak ,  Myoung-Won Yoon ,  Daeseok Byeon ,  Chiweon Yoon

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/16 ,  G11C16/26 ,  G11C16/04

CPC classification number: G11C16/3404 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3459 ,  G11C16/349 ,  G11C16/3495

Abstract: A storage device includes a nonvolatile memory device including memory blocks and a controller configured to control the nonvolatile memory device. Each of the memory blocks includes a plurality of cell strings each including at least one selection transistor and a plurality of memory cells stacked on a substrate in a direction perpendicular to the substrate. The controller controls the nonvolatile memory device to perform a read operation on some of selection transistors of a selected one of the memory blocks and to perform a program operation on the selection transistors of the selected memory block according to a result of the read operation.

公开(公告)号：US12278182B2

公开(公告)日：2025-04-15

申请号：US17721481

申请日：2022-04-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changyeon Yu ,  Pansuk Kwak ,  Daeseok Byeon

IPC: H01L23/528 ,  G11C16/08 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B41/50 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40 ,  H10B43/50

Abstract: A vertical memory device may include a first conductive line structure and an address decoder. The first conductive line structure may be on a substrate. The first conductive line structure may include conductive lines and insulation layers alternately and repeatedly stacked in a direction perpendicular to the substrate. The address decoder may be connected to a first end of each of conductive lines included in the first conductive line structure. The address decoder may apply electrical signal to the conductive lines. In each of the conductive lines, a first portion adjacent to the first end and a second portion adjacent to a second end may have different shapes. A first resistance in the first portion may be lower than a second resistance in the second portion. RC delay of the conductive lines may be reduced.

公开(公告)号：US12120881B2

公开(公告)日：2024-10-15

申请号：US16931500

申请日：2020-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bongsoon Lim ,  Daeseok Byeon

IPC: H10B43/40 ,  G11C7/18 ,  G11C8/14 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/46 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B43/40 ,  G11C7/18 ,  G11C8/14 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/46 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: Disclosed is a three-dimensional semiconductor device comprising channel regions that penetrate the stack structure and extend in a direction perpendicular to a top surface of the first substrate, a first interlayer dielectric layer on the stack structure, and a peripheral circuit structure on the first interlayer dielectric layer. The peripheral circuit structure includes peripheral circuit elements on a first surface of a second substrate. The peripheral circuit elements are electrically connected to the channel regions and at least one of the gate electrodes. The first substrate has a first crystal plane parallel to the top surface thereof. The second substrate has a second crystal plane parallel to the first surface thereof. An arrangement direction of atoms of the first crystal plane intersects an arrangement direction of atoms of the second crystal plane.

公开(公告)号：US12002512B2

公开(公告)日：2024-06-04

申请号：US17709910

申请日：2022-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changyeon Yu ,  Pansuk Kwak ,  Daeseok Byeon

IPC: G11C16/00 ,  G11C16/04 ,  G11C16/08

CPC classification number: G11C16/0483 ,  G11C16/08

Abstract: A semiconductor device includes a memory cell array including a plurality of memory blocks, each of the plurality of memory blocks including select transistors and memory cells; pass transistors configured to provide select signals to select lines connected to a selected memory block; and ground transistors configured to supply a first voltage to select lines connected to unselected memory blocks. The ground transistors include at least one common gate structure, at least one common active region, and individual active regions, and each of the common gate structure and the common active region are shared by two or more ground transistors, among the ground transistors. The common gate structure is between the common active region and the individual active regions, and includes a first region extending in a first direction and a second region extending in a second direction, intersecting the first direction.

公开(公告)号：US20240145013A1

公开(公告)日：2024-05-02

申请号：US18367799

申请日：2023-09-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongsung Cho ,  Insu Kim ,  Daeseok Byeon

IPC: G11C16/24 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30 ,  G11C16/34

CPC classification number: G11C16/24 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30 ,  G11C16/3459 ,  G11C16/32

Abstract: A memory device includes a memory cell array, and a page buffer circuit including a plurality of page buffers selectively connected to memory cells via a plurality of bit lines, each of the plurality of page buffers including a sensing node. The sensing nodes may be charged to different levels during verification of programming states of the memory cells. For example, a first sensing node of a first page buffer connected to a first memory cell targeted for programming to a first program state from among the plurality of page buffers is precharged to a first level in a first precharge period during verification of the first program state. A second sensing node of a second page buffer connected to a second memory cell targeted for programming to a second program state charged to a second level during verification of the second program state, wherein the second level is different from the first level.