公开(公告)号：US20150123701A1

公开(公告)日：2015-05-07

申请号：US14478344

申请日：2014-09-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Robert C. Bowen

IPC: H01L49/00 ,  H01L29/06 ,  H01L29/88 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L49/006 ,  H01L29/0669 ,  H01L29/1606 ,  H01L29/20 ,  H01L29/88

Abstract: A logic device is provided which includes an electron monochromator. The electron monochromator includes a quantum dot disposed between first and second tunneling barriers, an emitter coupled to the first tunneling barrier, and a collector coupled to the second tunneling barrier. The logic device also includes a quantum interference device. The quantum interference device includes a source which is coupled to the collector of the electron monochromator.

Abstract translation: 提供了一种包括电子单色仪的逻辑器件。 电子单色仪包括设置在第一和第二隧道势垒之间的量子点，耦合到第一隧道势垒的发射极和耦合到第二隧穿势垒的集电极。 逻辑器件还包括量子干涉器件。 量子干涉装置包括耦合到电子单色仪的集电极的源。

公开(公告)号：US20150123215A1

公开(公告)日：2015-05-07

申请号：US14270690

申请日：2014-05-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Jorge A. Kittl ,  Mark S. Rodder

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/51 ,  H01L29/20 ,  H01L29/49

CPC classification number: H01L29/42392 ,  H01L29/78681 ,  H01L29/78696

Abstract: A field effect transistor includes a body layer comprising a crystalline semiconductor channel region therein, and a gate stack on the channel region. The gate stack includes a crystalline semiconductor gate layer, and a crystalline semiconductor gate dielectric layer between the gate layer and the channel region. Related devices and fabrication methods are also discussed.

Abstract translation: 场效应晶体管包括其中包括晶体半导体沟道区的主体层，以及沟道区上的栅叠层。 栅极堆叠包括晶体半导体栅极层和栅极层和沟道区之间的晶体半导体栅极介电层。 还讨论了相关设备和制造方法。

公开(公告)号：US12260324B2

公开(公告)日：2025-03-25

申请号：US17133427

申请日：2020-12-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Jorge A. Kittl ,  Ryan Hatcher

IPC: G06N3/04 ,  G06N3/0442 ,  G06N3/063 ,  G06N3/065 ,  G11C11/54 ,  G11C11/56 ,  H10B20/00 ,  H10B41/27 ,  G06N3/045 ,  G11C13/00 ,  H01L21/762

Abstract: A neuromorphic weight cell (NWC) including a resistor ladder including a plurality of resistors connected in series, and a plurality of shunting nonvolatile memory (NVM) elements, each of the shunting NVM elements being coupled in parallel to a corresponding one of the resistors.

公开(公告)号：US11816563B2

公开(公告)日：2023-11-14

申请号：US16409487

申请日：2019-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Titash Rakshit ,  Ryan M. Hatcher ,  Jorge A. Kittl ,  Borna J. Obradovic ,  Engin Ipek

IPC: G06F11/07 ,  G06F11/10 ,  G06N3/08 ,  G06F17/16

CPC classification number: G06N3/08 ,  G06F17/16

Abstract: A method of storing a sparse weight matrix for a trained artificial neural network in a circuit including a series of clusters. The method includes partitioning the sparse weight matrix into at least one first sub-block and at least one second sub-block. The first sub-block includes only zero-value weights and the second sub-block includes non-zero value weights. The method also includes assigning the non-zero value weights in the at least one second sub-block to at least one cluster of the series of clusters of the circuit. The circuit is configured to perform matrix-vector-multiplication (MVM) between the non-zero value weights of the at least one second sub-block and an input vector during an inference process utilizing the artificial neural network. The sub-blocks containing all zero elements are power gated, thereby reducing overall energy consumption for inference.

公开(公告)号：US11586901B2

公开(公告)日：2023-02-21

申请号：US17094356

申请日：2020-11-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Mark S. Rodder

IPC: G06N3/063 ,  H01L29/808 ,  H01L27/11521 ,  H01L29/66 ,  H01L29/788 ,  H01L29/423 ,  H01L21/28

Abstract: A neuromorphic device for the analog computation of a linear combination of input signals, for use, for example, in an artificial neuron. The neuromorphic device provides non-volatile programming of the weights, and fast evaluation and programming, and is suitable for fabrication at high density as part of a plurality of neuromorphic devices. The neuromorphic device is implemented as a vertical stack of flash-like cells with a common control gate contact and individually contacted source-drain (SD) regions. The vertical stacking of the cells enables efficient use of layout resources.

公开(公告)号：US10957786B2

公开(公告)日：2021-03-23

申请号：US16282105

申请日：2019-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon Goo Hong ,  Borna J. Obradovic ,  Mark Stephen Rodder

IPC: H01L21/70 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/324 ,  H01L21/223 ,  H01L21/225 ,  H01L29/78 ,  H01L29/10 ,  H01L29/167

Abstract: A method of manufacturing a field effect transistor includes forming a fin on a substrate, forming source and drain electrodes on opposite sides of the fin, forming a gate stack on a channel portion of the fin between the source and drain electrodes, forming gate spacers on extension portions of the fin on opposite sides of the gate stack, removing at least portions of the gate spacers to expose the extension portions of the fin, and hydrogen annealing the extension portions of the fin. Following the hydrogen annealing of the extension portions of the fin, the channel portion of the fin has a first width and the extension portions of the fin have a second width greater than the first width.

公开(公告)号：US10860923B2

公开(公告)日：2020-12-08

申请号：US15488419

申请日：2017-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Mark S. Rodder

IPC: G06N3/063 ,  H01L29/808 ,  H01L27/11521 ,  H01L29/66 ,  H01L29/788 ,  H01L29/423 ,  H01L21/28

Abstract: A neuromorphic device for the analog computation of a linear combination of input signals, for use, for example, in an artificial neuron. The neuromorphic device provides non-volatile programming of the weights, and fast evaluation and programming, and is suitable for fabrication at high density as part of a plurality of neuromorphic devices. The neuromorphic device is implemented as a vertical stack of flash-like cells with a common control gate contact and individually contacted source-drain (SD) regions. The vertical stacking of the cells enables efficient use of layout resources.

公开(公告)号：US10854591B2

公开(公告)日：2020-12-01

申请号：US15442592

申请日：2017-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Titash Rakshit ,  Borna J. Obradovic ,  Chris Bowen ,  Mark S. Rodder

IPC: H01L27/12 ,  H01L21/66 ,  H01L23/522 ,  H01L27/02 ,  H01L21/8238 ,  H01L21/822 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L21/768 ,  H01L21/84 ,  H01L23/528 ,  H01L23/532 ,  H01L27/06 ,  H01L27/092 ,  H01L29/04 ,  H01L29/16 ,  H01L29/47 ,  H01L29/66

Abstract: A semiconductor device includes a series of metal routing layers and a complementary pair of planar field-effect transistors (FETs) on an upper metal routing layer of the metal routing layers. The upper metal routing layer is M3 or higher. Each of the FETs includes a channel region of a crystalline material. The crystalline material may include polycrystalline silicon. The upper metal routing layer M3 or higher may include cobalt.

公开(公告)号：US20200234114A1

公开(公告)日：2020-07-23

申请号：US16409487

申请日：2019-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Titash Rakshit ,  Ryan M. Hatcher ,  Jorge A. Kittl ,  Borna J. Obradovic ,  Engin Ipek

IPC: G06N3/08 ,  G06F17/16

Abstract: A method of storing a sparse weight matrix for a trained artificial neural network in a circuit including a series of clusters. The method includes partitioning the sparse weight matrix into at least one first sub-block and at least one second sub-block. The first sub-block includes only zero-value weights and the second sub-block includes non-zero value weights. The method also includes assigning the non-zero value weights in the at least one second sub-block to at least one cluster of the series of clusters of the circuit. The circuit is configured to perform matrix-vector-multiplication (MVM) between the non-zero value weights of the at least one second sub-block and an input vector during an inference process utilizing the artificial neural network. The sub-blocks containing all zero elements are power gated, thereby reducing overall energy consumption for inference.

公开(公告)号：US10700068B2

公开(公告)日：2020-06-30

申请号：US16227701

申请日：2018-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mark S. Rodder ,  Borna J. Obradovic

IPC: H01L21/00 ,  H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/04 ,  H01L21/84 ,  H01L29/10 ,  H01L27/12 ,  H01L29/66

Abstract: A field effect transistor (FET) for an nFET and/or a pFET device including a substrate and a fin including at least one channel region decoupled from the substrate. The FET also includes a source electrode and a drain electrode on opposite sides of the fin, and a gate stack extending along a pair of sidewalls of the channel region of the fin. The gate stack includes a gate dielectric layer and a metal layer on the gate dielectric layer. The FET also includes an oxide separation region separating the channel region of the fin from the substrate. The oxide separation region includes a dielectric material that includes a portion of the gate dielectric layer of the gate stack. The oxide separation region extends completely from a surface of the channel region facing the substrate to a surface of the substrate facing the channel region.