公开(公告)号：US10388367B2

公开(公告)日：2019-08-20

申请号：US15351552

申请日：2016-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Won Park ,  Dongkyo Shim ,  Kitae Park ,  Sang-Won Shim

IPC: G11C8/08 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  G11C16/34 ,  G11C29/02

Abstract: A nonvolatile memory device includes a voltage generator that sequentially provides a first setup voltage and second setup voltage to a word line of a memory cell array, and control logic including a time control unit that determines a word line setup time for the word line in relation to the second setup voltage based on a difference between the first and second setup voltages.

公开(公告)号：US10247867B2

公开(公告)日：2019-04-02

申请号：US15242862

申请日：2016-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joungeun Yoo ,  Dmitry Androsov ,  Changki Kim ,  Kitae Park

IPC: C08G73/10 ,  G02B5/30 ,  C07C211/51 ,  C07C229/60 ,  C08J5/18

Abstract: A monomer represented by Chemical Formula 1-1 wherein in Chemical Formula 1-1, Z, L1, L2, R1 to R6, n, m, p, and a to f are the same as defined in the detailed description.

公开(公告)号：US09767912B2

公开(公告)日：2017-09-19

申请号：US15172301

申请日：2016-06-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Wook Park ,  Kitae Park ,  Jaeyong Jeong

IPC: G11C16/04 ,  G11C16/14 ,  G11C16/34 ,  G11C11/56 ,  G11C16/08 ,  G11C16/26

CPC classification number: G11C16/14 ,  G11C11/56 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3445

Abstract: An method of operating a memory system including a plurality of memory cells includes changing an operation mode at least some of the memory cells which operate based on a first operation mode to operate based on a second operation mode; and performing a change erase operation on the memory cells for which an operation mode is changed on the basis of a change erase condition when the operation mode is changed. When memory cells operate in the first operation mode, a normal erase operation is performed based on a first erase condition, and when memory cells operate in the second operation mode, a normal erase operation is performed based on a second erase condition. The change erase condition is different from at least one of the first and second erase conditions.

公开(公告)号：US09588714B2

公开(公告)日：2017-03-07

申请号：US15219742

申请日：2016-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Wan Nam ,  Kitae Park

IPC: G06F11/00 ,  G06F3/06 ,  G11C16/34 ,  G06F11/10 ,  G11C29/52 ,  G06F11/14

CPC classification number: G06F3/0653 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1068 ,  G06F11/1402 ,  G11C11/5628 ,  G11C16/3445 ,  G11C16/3495 ,  G11C29/52

Abstract: In one embodiment, the method includes determining, at the memory controller, a status of a selected page of memory based on a program/erase cycle count for a block of the memory. The block of the memory includes the selected page. The program/erase cycle count indicates a number of times the block has been erased. The status is selected from a plurality of status states. The status states include a normal state, a weak state and a bad state.

Abstract translation: 在一个实施例中，该方法包括基于存储器块的编程/擦除周期计数在存储器控制器处确定所选择的存储器页的状态。 存储器的块包括所选择的页面。 程序/擦除周期计数指示块已被擦除的次数。 该状态是从多个状态中选择的。 状态包括正常状态，弱状态和坏状态。

公开(公告)号：US09466386B2

公开(公告)日：2016-10-11

申请号：US14336343

申请日：2014-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Wook Park ,  Jung-Soo Kim ,  Jaeyong Jeong ,  Kitae Park ,  Youngsun Song

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/22 ,  G11C16/10

CPC classification number: G11C16/225 ,  G11C16/0483 ,  G11C16/10

Abstract: A method of programming a storage device comprises determining whether at least one open page exists in a memory block of a nonvolatile memory device, and as a consequence of determining that at least one open page exists in the memory block, closing the at least one open page through a dummy pattern program operation, and thereafter performing a continuous writing operation on the memory block.

Abstract translation: 一种对存储设备进行编程的方法包括确定至少一个开放页面是否存在于非易失性存储器件的存储器块中，并且作为确定存储器块中存在至少一个打开页面的结果，关闭至少一个打开的 通过虚拟图案编程操作，然后对存储块进行连续写入操作。

公开(公告)号：US09251904B2

公开(公告)日：2016-02-02

申请号：US14458567

申请日：2014-08-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Doohyun Kim ,  Hyun Jun Yoon ,  Donghun Kwak ,  Kitae Park ,  Changyeon Yu

IPC: G11C29/56 ,  G11C16/26

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/3418 ,  G11C16/3495 ,  G11C29/52 ,  G11C29/56

Abstract: A nonvolatile memory device may include a memory cell array which is arranged in rows and columns and has multi-level memory cells; a voltage generator providing a plurality of read voltages to a selected row of the memory cell array; and control logic performing a plurality of page read operations using the read voltages. A first read voltage and a second read voltage among the plurality of read voltages are each associated with a higher probability of occurrence of a bit read error than at least one other read voltage among the plurality of read voltages. The control logic uses the first read voltage and the second read voltage in different page read operations than each other.

Abstract translation: 非易失性存储器件可以包括以行和列布置并具有多级存储单元的存储单元阵列; 电压发生器，向存储单元阵列的选定行提供多个读取电压; 以及控制逻辑，使用读取的电压执行多个页面读取操作。 多个读取电压之间的第一读取电压和第二读取电压各自与多个读取电压中的至少一个其他读取电压的比特读取错误的发生概率相关。 控制逻辑在彼此不同的页读操作中使用第一读电压和第二读电压。

公开(公告)号：US20150150971A1

公开(公告)日：2015-06-04

申请号：US14324818

申请日：2014-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun Min PARK ,  Jungyong Nam ,  Kitae Park ,  Hyun Ryoung Kim ,  Eun Sung Park

IPC: A61K41/00 ,  A61K31/704 ,  A61K9/127

CPC classification number: A61K31/704 ,  A61K9/0009 ,  A61K9/127 ,  A61K41/0033 ,  A61K47/26

Abstract: Provided is a liposome comprising a lipid bilayer and a sonosensitizer that is disposed in and/or on the lipid bilayer, wherein the sonosensitizer self-assembles to form aggregates when exposed to ultrasound; and a method of efficiently delivering an active agent to a target site in the body of a subject using the sonosensitive liposome.

Abstract translation: 本发明提供一种脂质体，其包含脂质双层和设置在脂质双层中和/或之上的超声敏敏剂，其中，当暴露于超声波时，所述超声敏敏剂自组装形成聚集体; 以及使用超声敏感脂质体将活性剂有效递送到受试者体内的靶位点的方法。

公开(公告)号：US08964468B2

公开(公告)日：2015-02-24

申请号：US14319137

申请日：2014-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangyong Yoon ,  Kitae Park ,  Jinman Han ,  Wonseok Lee

IPC: G11C16/04 ,  G11C16/10 ,  G11C14/00

CPC classification number: G11C16/10 ,  G11C11/56 ,  G11C11/5628 ,  G11C14/0018 ,  G11C16/0483 ,  G11C16/26 ,  G11C2211/5641 ,  G11C2211/5642 ,  G11C2211/5643

Abstract: A data storage device includes a non-volatile memory device which includes a memory cell array; and a memory controller which includes a buffer memory. The operating method of the data storage device includes storing data in the buffer memory, and determining whether the data stored in the buffer memory is data accompanying a buffer program operation of the memory cell array. When the data stored in the buffer memory is data accompanying the buffer program operation, the method further includes determining whether a main program operation on the memory cell array is required, and when a main program operation on the memory cell array is required, determining a program pattern of the main program operation on the memory cell array. The method further includes issuing a set of commands for the main program operation on the memory cell array to the multi-bit memory device based on the program pattern.

Abstract translation: 数据存储装置包括：非易失性存储装置，其包括存储单元阵列; 以及包括缓冲存储器的存储器控​​制器。 数据存储装置的操作方法包括将数据存储在缓冲存储器中，并且确定存储在缓冲存储器中的数据是否是伴随存储器单元阵列的缓冲器程序操作的数据。 当存储在缓冲存储器中的数据是伴随缓冲器程序操作的数据时，该方法还包括确定是否需要对存储单元阵列的主程序操作，以及当需要存储单元阵列的主程序操作时， 存储单元阵列中的主程序操作的程序模式。 该方法还包括基于该程序模式向存储单元阵列发出用于主程序操作的一组命令到多位存储器件。

公开(公告)号：US20240393326A1

公开(公告)日：2024-11-28

申请号：US18368284

申请日：2023-09-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Carlos Cristiano DE JESUS ALCANTARA ,  Mikyung Kim ,  Kitae Park ,  Chisung Bae ,  Jaechun Lee ,  Anes Ju

IPC: G01N33/543 ,  A61B5/1468

Abstract: There is disclosed an electrode including a substrate, a conductive material layer on the substrate, an insulating layer comprising an electrode layer on the conductive material layer, and a groove region in at least a portion of the insulating layer, and the electrode layer is extended into the groove region, and the conductive material layer is exposed to the groove region.

公开(公告)号：US20240355709A1

公开(公告)日：2024-10-24

申请号：US18637022

申请日：2024-04-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kitae Park ,  Seonkyu Kim ,  Seungmin Baek ,  Joonseok Oh ,  Joohyung Lee ,  Junghyun Cho

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/544 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L23/3128 ,  H01L23/544 ,  H01L24/16 ,  H01L25/0657 ,  H01L2223/54426 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1815

Abstract: A semiconductor package includes a base chip, a first semiconductor chip on the base chip, and a first fillet layer between the base chip and the first semiconductor chip. The base chip includes a base substrate, a plurality of through-electrodes penetrating through the base substrate, a protective layer surrounding the plurality of through-electrodes and covering an upper surface of the base substrate, and a plurality of trenches vertically penetrating the protective layer. The plurality of through-electrodes form a transistor area on the base substrate, and the plurality of trenches include first trenches disposed between adjacent through-vias in the transistor area and second trenches disposed in an outer side portion of the transistor area.