公开(公告)号：US12199163B2

公开(公告)日：2025-01-14

申请号：US18478373

申请日：2023-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Munhyeon Kim ,  Myung Gil Kang ,  Wandon Kim

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/49 ,  H01L29/786

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The device may include a substrate, an active pattern in an upper portion of the substrate and is extending in a first direction, a gate electrode crossing the active pattern and extending in a second direction intersecting the first direction, a first gate spacer covering a side surface of the gate electrode, a first inhibition layer between the gate electrode and the first gate spacer, and a gate insulating layer between the gate electrode and the active pattern. The gate insulating layer may include a high-k dielectric layer and a gate oxide layer. The gate oxide layer may be between the high-k dielectric layer and the active pattern. The high-k dielectric layer may be between the gate oxide layer and the gate electrode.

公开(公告)号：US12063767B2

公开(公告)日：2024-08-13

申请号：US17541790

申请日：2021-12-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Gil Kang ,  Seunghun Lee ,  Sangdeok Kwon ,  Keun Hwi Cho ,  Sung Gi Hur

IPC: H01L27/11 ,  H01L29/36 ,  H01L29/423 ,  H01L29/786 ,  H10B10/00

CPC classification number: H10B10/12 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device includes a first active pattern on a substrate, a pair of first source/drain patterns on the first active pattern and a first channel pattern between the pair of first source/drain patterns, wherein the first channel pattern includes a plurality of semiconductor patterns that are stacked and spaced apart from each other, a first gate electrode on the first channel pattern, a first gate cutting pattern that is adjacent to the first channel pattern and penetrates the first gate electrode, and a first residual pattern between the first gate cutting pattern and the first channel pattern. The first residual pattern covers an outermost sidewall of at least one semiconductor pattern of the plurality of semiconductor patterns of the first channel pattern. The first gate electrode includes, on an upper portion of the first gate electrode, a first extension that vertically overlaps the first residual pattern.

公开(公告)号：US20240234503A1

公开(公告)日：2024-07-11

申请号：US18465110

申请日：2023-09-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SOOJIN JEONG ,  Myung Gil Kang ,  Beomjim Park ,  Dongwon KIm ,  Younggwon Kim ,  Hyumin Yoo

IPC: H01L29/06 ,  H01L23/48 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L23/481 ,  H01L27/092 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate including first and second active regions, a first active pattern on the first active region, a second active pattern on the second active region, a device isolation layer filling a trench between the first active pattern and the second active pattern, the device isolation layer having a concave top surface, a first gate electrode in the first active region, a second gate electrode in the second active region, a gate cutting pattern disposed between the first gate electrode and the second gate electrode and separating the first gate electrode and the second gate electrode, and an insulating pattern between the gate cutting pattern and the concave top surface of the device isolation layer.

公开(公告)号：US20240079466A1

公开(公告)日：2024-03-07

申请号：US18136975

申请日：2023-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangwon Baek ,  Beomjin Park ,  Myung Gil Kang ,  Dongwon Kim ,  Hyumin Yoo ,  Namkyu Cho

IPC: H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/42392 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/775 ,  H01L2029/42388

Abstract: A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern, the channel pattern including a plurality of semiconductor patterns spaced apart from each other, a source/drain pattern connected to the plurality of semiconductor patterns, a gate electrode including, an inner electrode between a first semiconductor pattern of the plurality of semiconductor patterns and a second semiconductor pattern of the plurality of semiconductor patterns, the first semiconductor pattern and the second semiconductor pattern being adjacent to each other, and an outer electrode on an uppermost semiconductor pattern of the plurality of semiconductor patterns.

公开(公告)号：US20230411458A1

公开(公告)日：2023-12-21

申请号：US18239660

申请日：2023-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ilgyou Shin ,  Minyi Kim ,  Myung Gil Kang ,  Jinbum Kim ,  Seung Hun Lee ,  Keun Hwi Cho

IPC: H01L29/15 ,  H01L29/78 ,  H01L29/417 ,  H01L29/10

CPC classification number: H01L29/158 ,  H01L29/1033 ,  H01L29/41791 ,  H01L29/785

Abstract: A semiconductor device includes; a substrate including a first region and a second region, a first active pattern extending upward from the first region, a first superlattice pattern on the first active pattern, a first active fin centrally disposed on the first active pattern, a first gate electrode disposed on the first active fin, and first source/drain patterns disposed on opposing sides of the first active fin and on the first active pattern. The first superlattice pattern includes at least one first semiconductor layer and at least one first blocker-containing layer, and the first blocker-containing layer includes at least one of oxygen, carbon, fluorine and nitrogen.

公开(公告)号：US11804530B2

公开(公告)日：2023-10-31

申请号：US17245601

申请日：2021-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Munhyeon Kim ,  Myung Gil Kang ,  Wandon Kim

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/42364 ,  H01L29/0653 ,  H01L29/42368 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/78696

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The device may include a substrate, an active pattern in an upper portion of the substrate and is extending in a first direction, a gate electrode crossing the active pattern and extending in a second direction intersecting the first direction, a first gate spacer covering a side surface of the gate electrode, a first inhibition layer between the gate electrode and the first gate spacer, and a gate insulating layer between the gate electrode and the active pattern. The gate insulating layer may include a high-k dielectric layer and a gate oxide layer. The gate oxide layer may be between the high-k dielectric layer and the active pattern. The high-k dielectric layer may be between the gate oxide layer and the gate electrode.

公开(公告)号：US11769813B2

公开(公告)日：2023-09-26

申请号：US18046518

申请日：2022-10-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Gil Kang ,  Dong Won Kim ,  Woo Seok Park ,  Keun Hwi Cho ,  Sung Gi Hur

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/4236 ,  H01L29/78696

Abstract: Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction different from the first direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth.

公开(公告)号：US11695002B2

公开(公告)日：2023-07-04

申请号：US17720153

申请日：2022-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghoon Baek ,  Myung Gil Kang ,  Jae-Ho Park ,  Seung Young Lee

IPC: H01L27/02 ,  H01L27/092 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L27/118

CPC classification number: H01L27/0207 ,  H01L27/092 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696

Abstract: An integrated circuit includes first and second active regions, first and second standard cells on the first active region and the second active region, and a filler cell between the first and second standard cells and including first and second insulating isolations. The filler cell has a one-pitch dimension. The first and second insulating isolations are spaced the one-pitch dimension apart from each other. The first insulating isolation of the filler cell is disposed at a first boundary between the first standard cell and the filler cell. The second insulating isolation of the filler cell is disposed at a second boundary between the second standard cell and the filler cell. The first and second insulating isolations separate at least a part of the first active region, and at least a part of the second active region.

公开(公告)号：US20230080400A1

公开(公告)日：2023-03-16

申请号：US18051034

申请日：2022-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： KEUN HWI CHO ,  Soonmoon Jung ,  Dongwon Kim ,  Myung Gil Kang

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/417 ,  H01L23/528

Abstract: Semiconductor devices and methods of forming the same are disclosed. The semiconductor devices may include a substrate including a first region and a second region, which are spaced apart from each other with a device isolation layer interposed therebetween, a first gate electrode and a second gate electrode on the first and second regions, respectively, an insulating separation pattern separating the first gate electrode and the second gate electrode from each other and extending in a second direction that traverses the first direction, a connection structure electrically connecting the first gate electrode to the second gate electrode, and a first signal line electrically connected to the connection structure. The first and second gate electrodes are extended in a first direction and are aligned to each other in the first direction. The first signal line may extend in the second direction and may vertically overlap the insulating separation pattern.

公开(公告)号：US11482606B2

公开(公告)日：2022-10-25

申请号：US17209290

申请日：2021-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Gil Kang ,  Dong Won Kim ,  Woo Seok Park ,  Keun Hwi Cho ,  Sung Gi Hur

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/786 ,  H01L29/06

Abstract: Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction different from the first direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth.