公开(公告)号：US11152053B2

公开(公告)日：2021-10-19

申请号：US16994796

申请日：2020-08-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Hyuk Kwon ,  Nam Sung Kim ,  Kyomin Sohn ,  Seongil O ,  Haesuk Lee

IPC: G11C11/408 ,  G11C11/4074 ,  G11C11/4096 ,  G11C11/4094 ,  G11C7/10 ,  G11C11/406 ,  G11C8/12 ,  G11C11/4076

Abstract: A memory device includes a memory cell array including a plurality of banks each including a plurality of memory cells connected to a plurality of word lines, and a row decoder block connected to the plurality of banks. In a first operation mode, the row decoder block receives a first row address and a first bank address together with an activation command and activates a word line selected by the first row address from among the plurality of word lines of a bank selected by the first bank address from among the plurality of banks. In a second operation mode, the row decoder block receives a second row address and a second bank address together with the activation command and activates a word line selected by the second row address from among the plurality of word lines of each of at least two banks of the plurality of banks.

公开(公告)号：US20210287735A1

公开(公告)日：2021-09-16

申请号：US17333366

申请日：2021-05-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seongil O ,  Namsung KIM ,  Sukhan LEE

IPC: G11C11/4096 ,  G11C11/408 ,  G06F9/30 ,  G11C7/10 ,  G06F9/38 ,  G11C11/4091

Abstract: A high bandwidth memory and a system having the same are disclosed. The high bandwidth memory includes a buffer die and a plurality of memory dies, each of which includes at least one first processing element bank group and at least one second processing element bank group. The at least one first processing element bank group includes one or more first banks connected to one or more first bank input/output line groups, and a first processing element controller connected to the one or more first bank input/output line groups and a first global input/output line group, and is configured to perform a first processing operation on first data output from one of the one or more first bank input/output line groups and second data transmitted through the first global input/output line group based on a first instruction that is generated based on a first processing command.

公开(公告)号：US20210225430A1

公开(公告)日：2021-07-22

申请号：US16996434

申请日：2020-08-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seongil O

IPC: G11C11/4096 ,  H01L25/065 ,  G11C11/4091 ,  G06F13/16

Abstract: A memory die includes a first bank including first memory cells; a second bank including second memory cells; a first local processor connected with first bank local input/output lines through which first local bank data of the first bank are transmitted, and configured to execute a first local calculation on the first local bank data; a second local processor connected with second bank local input/output lines through which second local bank data of the second bank are transmitted, and configured to execute a second local calculation on the second local bank data; and a global processor configured to control the first bank, the second bank, the first local processor, and the second local processor and to execute a global calculation on a first local calculation result of the first local calculation and a second local calculation result of the second local calculation.

公开(公告)号：US10019367B2

公开(公告)日：2018-07-10

申请号：US15479795

申请日：2017-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongil O ,  Chankyung Kim ,  Jongpil Son

IPC: G06F12/08 ,  G06F12/0846 ,  G06F12/128 ,  G06F12/0844 ,  G06F12/0884

CPC classification number: G06F12/0846 ,  G06F11/1064 ,  G06F11/34 ,  G06F12/0246 ,  G06F12/0844 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/128 ,  G06F2201/885 ,  G06F2212/1032 ,  G06F2212/214 ,  G06F2212/313 ,  G06F2212/7201 ,  G11C5/04 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/40607 ,  G11C11/4093 ,  G11C11/4096 ,  G11C16/0483 ,  G11C16/32 ,  G11C29/26 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2029/5002 ,  G11C2207/2245

Abstract: A method includes outputting, at a processor, a command and an address to the memory module, receiving match/unmatch bits indicating results of comparing a tag corresponding to the address with tags stored in the memory module, from the memory module, determining, at the processor, a cache hit/miss from the match/unmatch bits by using majority voting, and outputting, at the processor, the determined cache hit/miss to the memory module.

公开(公告)号：US09971697B2

公开(公告)日：2018-05-15

申请号：US15354354

申请日：2016-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chankyung Kim ,  Uksong Kang ,  Sanguhn Cha ,  Sungyong Seo ,  Youngjin Cho ,  Seongil O

IPC: G06F12/08 ,  G06F12/0871 ,  G11C11/4093 ,  G11C7/10 ,  G06F12/0802 ,  G06F12/0853

CPC classification number: G06F12/0871 ,  G06F11/1064 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0853 ,  G06F12/0868 ,  G06F12/0895 ,  G06F2212/1004 ,  G06F2212/1028 ,  G06F2212/205 ,  G06F2212/214 ,  G06F2212/22 ,  G06F2212/313 ,  G06F2212/60 ,  G06F2212/601 ,  G06F2212/7203 ,  G11C5/04 ,  G11C7/1072 ,  G11C11/005 ,  G11C11/4093 ,  G11C16/0483

Abstract: A nonvolatile memory module includes at least one nonvolatile memory, at least one nonvolatile memory controller configured to control the nonvolatile memory, at least one dynamic random access memory (DRAM) used as a cache of the at least one nonvolatile memory, data buffers configured to store data exchanged between the at least one DRAM and an external device, and a memory module control device configured to control the nonvolatile memory controller, the at least one DRAM, and the data buffers. The at least one DRAM stores a tag corresponding to cache data and compares the stored tag with input tag information to determine whether to output the cache data.