公开(公告)号：US10074427B2

公开(公告)日：2018-09-11

申请号：US14539033

申请日：2014-11-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Idan Alrod ,  Noam Presman ,  Ariel Navon ,  Tz-Yi Liu ,  Tianhong Yan

IPC: G11C13/00 ,  G11C7/10

CPC classification number: G11C13/0097 ,  G11C7/1006 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0085 ,  G11C2213/77

Abstract: A method includes, in a data storage device including a resistive memory, receiving, from an external device, an erase command to erase a portion of the resistive memory. The method further includes storing shaped data at the portion of the resistive memory responsive to the erase command. Shaped data is configured to control an amount of leakage current during a read and/or write operation at one or more storage elements that are adjacent to at least one storage element of the portion of the resistive memory.

公开(公告)号：US20180203762A1

公开(公告)日：2018-07-19

申请号：US15921165

申请日：2018-03-14

Applicant: SanDisk Technologies LLC

Inventor： Idan Alrod ,  Eran Sharon ,  Alon Eyal ,  Liang Pang ,  Evgeny Mekhanik

IPC: G06F11/10 ,  G11C29/52 ,  G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G11C16/26 ,  G11C16/08

CPC classification number: G06F11/1068 ,  G06F11/08 ,  G06F11/10 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3459 ,  G11C29/52 ,  G11C2207/2281

Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. A memory cell is sensed by discharging a sense node into a bit line and detecting an amount of discharge at two sense times relative to a trip voltage. A bit of data is stored in first and second latches based on the two sense times, to provide first and second pages of data. The pages are evaluated using parity check equations and one of the pages which satisfies the most equations is selected. In another option, word line voltages are grounded and then floated to prevent coupling up of the word line. A weak pulldown to ground can gradually discharge a coupled up voltage of the word lines.

公开(公告)号：US10002649B1

公开(公告)日：2018-06-19

申请号：US15440975

申请日：2017-02-23

Applicant: SanDisk Technologies LLC

Inventor： Ronen Golan ,  Roie Shpaizman ,  Alex Bazarsky ,  Eli Elmoalem ,  Grishma Shah ,  Idan Alrod

IPC: G11C7/10 ,  G11C16/32 ,  G11C7/22

CPC classification number: G11C7/1063 ,  G11C7/22 ,  G11C16/10 ,  G11C16/32 ,  G11C16/3459

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for providing a preliminary ready indication for non-volatile memory. A non-volatile memory element initiates a write operation for one or more storage cells of the non-volatile memory element. The non-volatile memory element determines whether a progress threshold is satisfied for the write operation. The non-volatile memory element provides a preliminary ready indication, indicating that the progress threshold is satisfied.

公开(公告)号：US09947399B2

公开(公告)日：2018-04-17

申请号：US14669731

申请日：2015-03-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ariel Navon ,  Idan Alrod ,  Eran Sharon ,  Idan Goldenberg ,  Didi Gur

IPC: G06F11/10 ,  G11C13/00 ,  G11C29/52

CPC classification number: G11C13/0069 ,  G06F11/1048 ,  G06F11/1056 ,  G06F11/1068 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0097 ,  G11C29/52 ,  G11C2013/0076 ,  G11C2013/0085

Abstract: Data is initially programmed in a portion of ReRAM in parallel. Subsequently, one or more ReRAM cells in the portion are determined to contain first data that is to be modified while remaining ReRAM cells in the portion contain second data that is not to be modified. First conditions are applied to the one or more ReRAM cells thereby modifying the first data, while second conditions are applied to the remaining ReRAM cells, the second conditions maintaining the second data in the remaining ReRAM cells without significant change.

公开(公告)号：US09946468B2

公开(公告)日：2018-04-17

申请号：US15459578

申请日：2017-03-15

Applicant: SanDisk Technologies LLC

Inventor： Kevin Michael Conley ,  Raul-Adrian Cernea ,  Eran Sharon ,  Idan Alrod

IPC: G11C16/26 ,  G06F3/06 ,  G11C11/56 ,  G11C16/08 ,  G11C16/04 ,  G11C16/34 ,  G06F11/10 ,  G11C29/52

CPC classification number: G06F3/061 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1012 ,  G06F11/1068 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/107 ,  G11C16/3459 ,  G11C29/52

Abstract: A non-volatile memory system including multi-level storage optimized for ramp sensing and soft decoding is provided. Sensing is performed at a higher bit resolution than an original user data encoding to improve the accuracy of reading state information from non-volatile storage elements. Higher resolution state information is used for decoding the original user data to improve read performance through improved error handling. Ramp sensing is utilized to determine state information by applying a continuous input scanning sense voltage that spans a range of read compare points. Full sequence programming is enabled as is interleaved coding of the user data over all of the data bit sets associated with the storage elements.