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    Dynamic per-decoder control of log likelihood ratio and decoding parameters
    41.
    发明授权
    Dynamic per-decoder control of log likelihood ratio and decoding parameters 有权
    动态每解码器控制对数似然比和解码参数

    公开(公告)号：US09213600B2

    公开(公告)日：2015-12-15

    申请号：US14092215

    申请日：2013-11-27

    Applicant: Seagate Technology LLC

    Inventor： Earl T. Cohen ,  Yunxiang Wu ,  Alexander Hubris ,  Christopher Brewer

    IPC: H03M13/11 ,  G06F11/10

    CPC classification number: G06F11/1068 ,  G11C29/52 ,  H03M13/45

    Abstract: An apparatus includes one or more error-correction decoders, a buffer, at least one direct memory access (DMA) engine, and at least one processor. The buffer may be configured to store data to be decoded by the one or more error-correction decoders. The at least one DMA engine may couple the buffer and the one or more error-correction decoders. The at least one processor may be enabled to send messages to the at least one DMA engine. The messages may be configured to deliver DMA control information and corresponding datapath control information. Data may be read from the buffer based upon the DMA control information and delivered to the one or more error-correction decoders along with the corresponding datapath control information. The one or more error-correction decoders may be enabled to decode the data read from the buffer according to the corresponding datapath control information.

    Abstract translation: 一种装置包括一个或多个纠错解码器，缓冲器，至少一个直接存储器访问（DMA）引擎和至少一个处理器。 缓冲器可以被配置为存储要由一个或多个纠错解码器解码的数据。 至少一个DMA引擎可以耦合缓冲器和一个或多个纠错解码器。 可以使至少一个处理器能够向至少一个DMA引擎发送消息。 消息可以被配置为递送DMA控制信息和相应的数据路径控制信息。 可以基于DMA控制信息从缓冲器读取数据，并将其与相应的数据路径控制信息一起递送到一个或多个纠错解码器。 可以使一个或多个纠错解码器根据相应的数据路径控制信息解码从缓冲器读取的数据。

    PARTIAL R-BLOCK RECYCLING
    42.
    发明申请
    PARTIAL R-BLOCK RECYCLING 审中-公开
    部分R块回收

    公开(公告)号：US20150134894A1

    公开(公告)日：2015-05-14

    申请号：US14602481

    申请日：2015-01-22

    Applicant: Seagate Technology LLC

    Inventor： Leonid Baryudin ,  Alex G. Tang ,  Earl T. Cohen

    IPC: G06F12/02

    CPC classification number: G06F12/0246 ,  G06F11/0793 ,  G06F11/1008 ,  G06F12/02 ,  G06F2211/109 ,  G06F2212/7205 ,  G11C16/3418 ,  G11C29/82 ,  G11C2029/0409 ,  G11C2029/0411

    Abstract: An apparatus includes a non-volatile memory and a controller. The non-volatile memory includes a plurality of R-blocks. The controller is coupled to the non-volatile memory. The controller is configured to (i) write data using the R-blocks as a unit of allocation and (ii) perform recycling operations selectively on either an entire one of the R-blocks or a portion less than all of one of the R-blocks.

    Abstract translation: 一种装置包括非易失性存储器和控制器。 非易失性存储器包括多个R块。 控制器耦合到非易失性存储器。 控制器被配置为（i）使用R块作为分配单元来写入数据，以及（ii）选择性地在R块中的整个R块或小于全部R块中的一部分执行再循环操作 块。

    METHOD OF WRITING AND READING DATA IN AN NVM USING LPAGE IDENTIFICATION HEADERS
    43.
    发明申请
    METHOD OF WRITING AND READING DATA IN AN NVM USING LPAGE IDENTIFICATION HEADERS 审中-公开

    公开(公告)号：US20200333969A1

    公开(公告)日：2020-10-22

    申请号：US16923655

    申请日：2020-07-08

    Applicant: Seagate Technology LLC

    Inventor： Earl T. Cohen

    IPC: G06F3/06 ,  G06F12/02 ,  G06F12/1009

    Abstract: A method includes the steps of storing a logical page (Lpage) identification header in each starting read unit of a non-volatile memory (NVM), a starting read unit defined as a first read unit in an Lpage, the Lpage comprising a plurality of contiguous sectors of data present in the NVM; reading a table with an address mapping function of a storage controller in communication with the NVM; and responsive to the step of reading the table, referencing an Lpage by a read unit address. A size of the table is thereby smaller than a size of a conventional table that must store a byte address of every read unit in the NVM, the smaller size of the table resulting in greater efficiency in reading the table over reading the conventional table.

    NON-VOLATILE MEMORY PROGRAM FAILURE RECOVERY VIA REDUNDANT ARRAYS
    44.
    发明申请
    NON-VOLATILE MEMORY PROGRAM FAILURE RECOVERY VIA REDUNDANT ARRAYS 审中-公开

    公开(公告)号：US20200019463A1

    公开(公告)日：2020-01-16

    申请号：US16580361

    申请日：2019-09-24

    Applicant: Seagate Technology LLC

    Inventor： Jeremy Isaac Nathaniel Werner ,  Earl T. Cohen

    IPC: G06F11/10 ,  G11C29/52 ,  G06F3/06 ,  G06F11/20

    Abstract: Methods, systems and computer-readable storage media for requesting programming of N portions of a plurality of non-volatile memories (NVMs) in accordance with received data. Redundancy information sufficient to recover from failures of M of the N portions for which programming was requested is updated in response to the requesting programming. Upon identifying one to M of the N portions that have failed the programming, re-programming of the one to M of the N portions is requested in accordance with data calculated based at least in part on the redundancy information.

    I/O device and computing host interoperation
    45.
    发明授权
    I/O device and computing host interoperation 有权

    公开(公告)号：US10514864B2

    公开(公告)日：2019-12-24

    申请号：US15661079

    申请日：2017-07-27

    Applicant: Seagate Technology LLC

    Inventor： Earl T. Cohen ,  Timothy L. Canepa

    IPC: G06F12/1027 ,  G06F3/06 ,  G06F12/00

    Abstract: Methods, systems and computer-readable storage media for receiving, via an external interface of a storage device, a command from a computing host, the command including at least one non-standard command modifier, executing the command according to a particular non-standard command modifier, storing an indication of the particular non-standard command modifier in an entry of a map associated with a logical block address of the command, and storing a shadow copy of the map in a memory of the computing host.

    DEVICE QUALITY METRICS USING UNSATISFIED PARITY CHECKS
    50.
    发明申请
    DEVICE QUALITY METRICS USING UNSATISFIED PARITY CHECKS 审中-公开
    使用不合格的奇偶性检查的设备质量度量

    公开(公告)号：US20170039098A1

    公开(公告)日：2017-02-09

    申请号：US15297574

    申请日：2016-10-19

    Applicant: Seagate Technology LLC

    Inventor： AbdelHakim S. Alhussien ,  Earl T. Cohen ,  Erich F. Haratsch

    IPC: G06F11/07

    CPC classification number: G06F11/076 ,  G06F11/0727 ,  G06F11/079 ,  G06F11/1068 ,  G06F11/3037 ,  G06F11/3065 ,  G11B20/1833 ,  G11B2020/185 ,  H03M13/1108 ,  H03M13/1128 ,  H03M13/114 ,  H03M13/3753 ,  H03M13/612 ,  H03M13/6516

    Abstract: An apparatus includes a memory and a controller. The memory may be configured to store data. The controller may be configured to process a plurality of read/write operations to/from the memory, receive a codeword from the memory, generate a plurality of syndromes of the codeword at a plurality of possible code rates, generate a plurality of count values by counting a number of unsatisfied parity checks in each of the plurality of syndromes, generate a plurality of normalized values by dividing the plurality of count values by a plurality of lengths of the plurality of possible code rates respectively, and determine a bit error rate value of the memory based on a lowest value among the plurality of normalized values.

    Abstract translation: 一种装置包括存储器和控制器。 存储器可以被配置为存储数据。 控制器可以被配置为处理对存储器的多个读/写操作，从存储器接收码字，以多个可能的代码速率生成码字的多个综合器，通过以下方式生成多个计数值： 对多个综合征中的每一个中的多个不满足的奇偶校验进行计数，分别通过将多个计数值除以多个可能代码率的多个长度来生成多个归一化值，并且确定 所述存储器基于所述多个归一化值中的最低值。

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