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41.发明申请Power-performance modulation in caches using a smart least recently used scheme 失效使用智能最近最近使用的方案在高速缓存中进行功率性能调制公开(公告)号：US20070260818A1
公开(公告)日：2007-11-08
申请号：US11418883
申请日：2006-05-04
IPC分类号： G06F12/00
CPC分类号： G06F12/0864 , G06F12/123 , G06F2212/1028 , G06F2212/601 , Y02D10/13
摘要： The number of ways in an N-way set associative sequential cache is modulated to trade power and performance. Way selection is restricted during the allocation based on address so that only a subset of the N-ways is used for a range of addresses allowing the N-ways that are not in use to be powered off.
摘要翻译： N路集合关联顺序高速缓存中的方式的数量被调制以交易功率和性能。 在基于地址的分配期间，路由选择被限制，使得只有N个路径的子集被用于允许不使用的N路被关闭的一系列地址。
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公开(公告)号：US07136992B2
公开(公告)日：2006-11-14
申请号：US10739689
申请日：2003-12-17
IPC分类号： G06F9/38
CPC分类号： G06F9/3802 , G06F9/325 , G06F9/3808 , G06F9/3844
摘要： A method and apparatus for a loop predictor for predicting the end of a loop is disclosed. In one embodiment, the loop predictor may have a predict counter to hold a predict count representing the expected number of times that a predictor stew value will repeat during the execution of a given loop. The loop predictor may also have one or more running counters to hold a count of the times that the stew value has repeated during the execution of the present loop. When the counter values match the predictor may issue a prediction that the loop will end.
摘要翻译： 公开了一种用于预测环路结束的环路预测器的方法和装置。 在一个实施例中，环路预测器可以具有预测计数器，以保持预测计数，该预测计数表示在给定循环的执行期间预测器炖值将重复的预期次数。 循环预测器还可以具有一个或多个运行计数器，以在执行当前循环期间保持炖煮值重复的次数的计数。 当计数器值匹配时，预测器可以发出循环结束的预测。
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公开(公告)号：US06718440B2
公开(公告)日：2004-04-06
申请号：US09966587
申请日：2001-09-28
IPC分类号： G06F1200
CPC分类号： G06F9/3802 , G06F9/383 , G06F12/0862 , G06F2212/6028
摘要： A request hint is issued prior to or while identifying whether requested data and/or one or more instructions are in a first memory. A second memory is accessed to fetch data and/or one or more instructions in response to the request hint. The data and/or instruction(s) accessed from the second memory are stored in a buffer. If the requested data and/or instruction(s) are not in the first memory, the data and/or instruction(s) are returned from the buffer.
摘要翻译： 在识别所请求的数据和/或一个或多个指令是否在第一存储器中之前或之前发出请求提示。 访问第二存储器以响应于请求提示来获取数据和/或一个或多个指令。 从第二存储器访问的数据和/或指令被存储在缓冲器中。 如果请求的数据和/或指令不在第一存储器中，则从缓冲器返回数据和/或指令。
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44.发明授权公开(公告)号：US06678810B1
公开(公告)日：2004-01-13
申请号：US09475363
申请日：1999-12-30
IPC分类号： G06F1300
CPC分类号： G06F9/3836 , G06F9/30043 , G06F9/30047 , G06F9/30087 , G06F9/3012 , G06F9/30145 , G06F9/3808 , G06F9/3812 , G06F9/3834 , G06F9/3855 , G06F9/3857 , G06F9/3867 , G06F2009/45583 , G06F2009/45591
摘要： A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.
摘要翻译： 一种用于防止内存访问的系统和方法。 存储器负载可以围栏，或者所有内存访问都可以被围起来。 系统接收一个将内存访问指令分为较早访问和较新访问的防护指令。 存储器排序单元内的缓冲器被分配给该指令。 比栅栏指令更新的访问指令会停止。 旧的访问指令已逐渐退出。 当所有较旧的内存访问都已停用时，从缓冲区中分派防护指令。
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45.发明授权公开(公告)号：US06651151B2
公开(公告)日：2003-11-18
申请号：US10194531
申请日：2002-07-12
IPC分类号： G06F1214
CPC分类号： G06F9/3836 , G06F9/30043 , G06F9/30047 , G06F9/30087 , G06F9/3012 , G06F9/30145 , G06F9/3808 , G06F9/3812 , G06F9/3834 , G06F9/3855 , G06F9/3857 , G06F9/3867 , G06F2009/45583 , G06F2009/45591
摘要： A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.
摘要翻译： 一种用于防止内存访问的系统和方法。 存储器负载可以围栏，或者所有内存访问都可以被围起来。 系统接收一个将内存访问指令分为较早访问和较新访问的防护指令。 存储器排序单元内的缓冲器被分配给该指令。 比栅栏指令更新的访问指令被停止。 旧的访问指令已逐渐退出。 当所有较旧的内存访问都已停用时，从缓冲区中分派防护指令。
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公开(公告)号：US20180308206A1
公开(公告)日：2018-10-25
申请号：US15698217
申请日：2017-09-07
申请人： Prasoonkumar Surti , Narayan Srinivasa , Feng Chen , Joydeep Ray , Ben J. Ashbaugh , Nicolas C. Galoppo Von Borries , Eriko Nurvitadhi , Balaji Vembu , Tsung-Han Lin , Kamal Sinha , Rajkishore Barik , Sara S. Baghsorkhi , Justin E. Gottschlich , Altug Koker , Nadathur Rajagopalan Satish , Farshad Akhbari , Dukhwan Kim , Wenyin Fu , Travis T. Schluessler , Josh B. Mastronarde , Linda L. Hurd , John H. Feit , Jeffery S. Boles , Adam T. Lake , Karthik Vaidyanathan , Devan Burke , Subramaniam Maiyuran , Abhishek R. Appu
发明人： Prasoonkumar Surti , Narayan Srinivasa , Feng Chen , Joydeep Ray , Ben J. Ashbaugh , Nicolas C. Galoppo Von Borries , Eriko Nurvitadhi , Balaji Vembu , Tsung-Han Lin , Kamal Sinha , Rajkishore Barik , Sara S. Baghsorkhi , Justin E. Gottschlich , Altug Koker , Nadathur Rajagopalan Satish , Farshad Akhbari , Dukhwan Kim , Wenyin Fu , Travis T. Schluessler , Josh B. Mastronarde , Linda L. Hurd , John H. Feit , Jeffery S. Boles , Adam T. Lake , Karthik Vaidyanathan , Devan Burke , Subramaniam Maiyuran , Abhishek R. Appu
CPC分类号： G06T1/20 , G06F3/0613 , G06F3/0659 , G06F3/0679 , G06F3/1438 , G06N3/0445 , G06N3/0454 , G06N3/063 , G06N3/08 , G06N3/084 , G06T1/60 , G09G5/001 , G09G5/363 , G09G2352/00 , G09G2360/06 , G09G2360/08 , G09G2360/121 , G09G2360/123 , G09G2370/08
摘要： An apparatus to facilitate compute optimization is disclosed. The apparatus includes a memory device including a first integrated circuit (IC) including a plurality of memory channels and a second IC including a plurality of processing units, each coupled to a memory channel in the plurality of memory channels.
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公开(公告)号：US20170178384A1
公开(公告)日：2017-06-22
申请号：US14976122
申请日：2015-12-21
摘要： Reducing SIMD fragmentation for SIMD execution widths of 32 or even 64 channels in a single hardware thread leads to better EU utilization. Increasing SIMD execution widths to 32 or 64 channels per thread, enables handling more vertices, patches, primitives and triangles per EU hardware thread. Modified 3D pipeline shader payloads can handle multiple patches in case of domain shaders or multiple primitives when primitive object instance count is greater than one in the case of geometry shaders and multiple triangles in case of pixel shaders.
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公开(公告)号：US20170178370A1
公开(公告)日：2017-06-22
申请号：US14976214
申请日：2015-12-21
摘要： A pixel input is divided into blocks. The a number of blocks is determined based on the maximum number of partial spans. Finally, the blocks are rasterized.
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公开(公告)号：US20170178274A1
公开(公告)日：2017-06-22
申请号：US14976306
申请日：2015-12-21
CPC分类号： G06F9/46 , G06F8/41 , G06F9/50 , G06F12/0842 , G06F2209/507 , G06T1/60 , G06T15/005 , G06T17/20
摘要： To use SIMD lanes efficiently for domain shader execution, domain point data from different domain shader patches may be packed together into a single SIMD thread. To generate an efficient code sequence, each domain point occupies one SIMD lane and all attributes for the domain point reside in their own partition of General Register File (GRF) space. This technique is called the multiple-patch SIMD dispatch mode.
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公开(公告)号：US09383998B2
公开(公告)日：2016-07-05
申请号：US13440096
申请日：2012-04-05
CPC分类号： G06F9/3836 , G06F9/30043 , G06F9/30047 , G06F9/30087 , G06F9/3012 , G06F9/30145 , G06F9/3808 , G06F9/3812 , G06F9/3834 , G06F9/3855 , G06F9/3857 , G06F9/3867 , G06F2009/45583 , G06F2009/45591
摘要： A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.
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