公开(公告)号：US20200258897A1

公开(公告)日：2020-08-13

申请号：US16786463

申请日：2020-02-10

Applicant: Sunrise Memory Corporation

Inventor： Tianhong Yan ,  Scott Brad Herner ,  Jie Zhou ,  Wu-Yi Henry Chien ,  Eli Harari

IPC: H01L27/11573 ,  H01L27/11582 ,  H01L29/45 ,  H01L23/528 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/225 ,  H01L29/786 ,  H01L29/66 ,  H01L27/11565

Abstract: A memory circuit includes: (i) a semiconductor substrate having a planar surface, the semiconductor substrate having formed therein circuitry for memory operations; (ii) a memory array formed above the planar surface, the memory array having one or more electrodes to memory circuits in the memory array, the conductors each extending along a direction substantially parallel to the planar surface; and (iii) one or more transistors each formed above, alongside or below a corresponding one of the electrodes but above the planar surface of the semiconductor substrate, each transistor (a) having first and second drain/source region and a gate region each formed out of a semiconductor material, wherein the first drain/source region, the second drain/source region or the gate region has formed thereon a metal silicide layer, and (b) selectively connecting the corresponding electrode to the circuitry for memory operations.

公开(公告)号：US20200176468A1

公开(公告)日：2020-06-04

申请号：US16703663

申请日：2019-12-04

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Scott Brad Herner ,  Wu-Yi Henry Chien ,  Jie Zhou ,  Eli Harari

IPC: H01L27/11582 ,  H01L21/308 ,  H01L29/66

Abstract: Various methods overcome the limitations and achieve superior scaling by (i) replacing a single highly challenging high aspect ratio etch step with two or more etch steps of less challenging aspect ratios and which involve wider and more mechanically stable active strips, (ii) using dielectric pillars for support and to maintain structural stability during a high aspect ratio etch step and subsequent processing steps, or (iii) using multiple masking steps to provide two or more etch steps of less challenging aspect ratios and which involve wider and more mechanically stable active strips.

公开(公告)号：US20200051990A1

公开(公告)日：2020-02-13

申请号：US16509282

申请日：2019-07-11

Applicant: Sunrise Memory Corporation

Inventor： Eli Harari ,  Raul Adrian Cernea ,  George Samachisa ,  Wu-Yi Henry Chien

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C16/04 ,  G11C11/56 ,  H01L27/06 ,  H01L27/12

Abstract: A thin-film storage transistor includes (a) first and second polysilicon layers of a first conductivity serving, respectively, as a source terminal and a drain terminal of the thin-film storage transistor; (b) a third polysilicon layer of a second conductivity adjacent the first and second polysilicon layers, serving as a channel region of the thin-film storage transistor; (c) a conductor serving as a gate terminal of the thin-film storage transistor; and (d) a charge-trapping region between the conductor and third polysilicon layer, wherein a fourth body layer polysilicon of the second conductivity is included to provide an alternative source of free charge careers to accelerate device operation.

公开(公告)号：US20240357817A1

公开(公告)日：2024-10-24

申请号：US18759218

申请日：2024-06-28

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Eli Harari ,  Wu-Yi Henry Chien ,  Scott Brad Herner

IPC: H10B43/27 ,  H01L21/28 ,  H01L21/768 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L21/76837 ,  H01L21/76843 ,  H01L29/40117 ,  H10B43/35

Abstract: A method to ease the fabrication of high aspect ratio three dimensional memory structures for memory cells with feature sizes of 20 nm or less, or with a high number of memory layers. The present invention also provides an improved isolation between adjacent memory cells along the same or opposite sides of an active strip. The improved isolation is provided by introducing a strong dielectric barrier film between adjacent memory cells along the same side of an active strip, and by staggering memory cells of opposite sides of the active strip.

公开(公告)号：US20240099003A1

公开(公告)日：2024-03-21

申请号：US18499091

申请日：2023-10-31

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Scott Brad Herner ,  Wu-Yi Henry Chien ,  Jie Zhou ,  Eli Harari

IPC: H10B43/27 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H10B43/27 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/31116

Abstract: A method for forming 3-dimensional vertical NOR-type memory string arrays uses damascene local bit lines is provided. The method of the present invention also avoids ribboning by etching local word lines in two steps. By etching the local word lines in two steps, the aspect ratio in the patterning and etching of stack of local word lines (“word line stacks”) is reduced, which improves the structural stability of the word line stacks.

公开(公告)号：US11917821B2

公开(公告)日：2024-02-27

申请号：US17527972

申请日：2021-11-16

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Vinod Purayath ,  Wu-Yi Henry Chien

IPC: H10B43/20 ,  H10B41/20

CPC classification number: H10B43/20 ,  H10B41/20

Abstract: In the highly efficient fabrication processes for HNOR arrays provided herein, the channel regions of the storage transistors in the HNOR arrays are protected by a protective layer after deposition until the subsequent deposition of a charge-trapping material before forming local word lines. Both the silicon for the channel regions and the protective material may be deposited in amorphous form and are subsequently crystallized in an anneal step. The protective material may be silicon boron, silicon carbon or silicon germanium. The protective material induces greater grain boundaries in the crystallized silicon in the channel regions, thereby providing greater charge carrier mobility, greater conductivity and greater current densities.

公开(公告)号：US11910612B2

公开(公告)日：2024-02-20

申请号：US17804986

申请日：2022-06-01

Applicant: SunRise Memory Corporation

Inventor： Tianhong Yan ,  Scott Brad Herner ,  Jie Zhou ,  Wu-Yi Henry Chien ,  Eli Harari

IPC: H10B43/40 ,  H01L29/45 ,  H01L23/528 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/225 ,  H01L29/786 ,  H01L29/66 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B43/40 ,  H01L21/0217 ,  H01L21/02164 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/2251 ,  H01L21/31111 ,  H01L21/32053 ,  H01L23/528 ,  H01L29/458 ,  H01L29/665 ,  H01L29/66742 ,  H01L29/78642 ,  H10B43/10 ,  H10B43/27

Abstract: A memory circuit includes: (i) a semiconductor substrate having a planar surface, the semiconductor substrate having formed therein circuitry for memory operations; (ii) a memory array formed above the planar surface, the memory array having one or more electrodes to memory circuits in the memory array, the conductors each extending along a direction substantially parallel to the planar surface; and (iii) one or more transistors each formed above, alongside or below a corresponding one of the electrodes but above the planar surface of the semiconductor substrate, each transistor (a) having first and second drain/source region and a gate region each formed out of a semiconductor material, wherein the first drain/source region, the second drain/source region or the gate region has formed thereon a metal silicide layer; and (b) selectively connecting the corresponding electrode to the circuitry for memory operations.

公开(公告)号：US11844217B2

公开(公告)日：2023-12-12

申请号：US17669024

申请日：2022-02-10

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Scott Brad Herner ,  Wu-Yi Henry Chien ,  Jie Zhou ,  Eli Harari

IPC: H10B43/27 ,  H01L21/3213 ,  H01L21/311

CPC classification number: H10B43/27 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/31116

Abstract: A method for forming 3-dimensional vertical NOR-type memory string arrays uses damascene local bit lines is provided. The method of the present invention also avoids ribboning by etching local word lines in two steps. By etching the local word lines in two steps, the aspect ratio in the patterning and etching of stack of local word lines (“word line stacks”) is reduced, which improves the structural stability of the word line stacks.

公开(公告)号：US11729980B2

公开(公告)日：2023-08-15

申请号：US17690943

申请日：2022-03-09

Applicant: SunRise Memory Corporation

Inventor： Eli Harari ,  Scott Brad Herner ,  Wu-Yi Henry Chien

IPC: H01L21/00 ,  H10B43/27 ,  H01L21/768 ,  H01L23/00 ,  H10B43/20 ,  H01L21/311 ,  G11C16/04

CPC classification number: H10B43/27 ,  H01L21/7682 ,  H01L21/76802 ,  H01L23/562 ,  H10B43/20 ,  G11C16/0466 ,  H01L21/31111

Abstract: A method addresses low cost, low resistance metal interconnects and mechanical stability in a high aspect ratio structure. According to the various implementations disclosed herein, a replacement metal process, which defers the need for a metal etching step in the fabrication process until after all patterned photoresist is no longer present. Under this process, the conductive sublayers may be both thick and numerous. The present invention also provides for a strut structure which facilitates etching steps on high aspect ratio structures, which enhances mechanical stability in a high aspect ratio memory stack.

公开(公告)号：US11705496B2

公开(公告)日：2023-07-18

申请号：US17222082

申请日：2021-04-05

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Wu-Yi Henry Chien ,  Scott Brad Herner ,  Eli Harari

IPC: H01L29/423 ,  H01L29/792 ,  H01L29/786 ,  H10B43/30

CPC classification number: H01L29/42348 ,  H01L29/78642 ,  H01L29/78672 ,  H01L29/7926 ,  H10B43/30

Abstract: A thin-film memory transistor includes a source region, a drain region, a channel region, a gate electrode, and a charge-trapping layer provided between the channel region and the gate electrode and electrically isolated therefrom, wherein the charge-trapping layer has includes a number of charge-trapping sites that is 70% occupied or evacuated using a single voltage pulse of a predetermined width of 500 nanoseconds or less and a magnitude of 15.0 volts or less. The charge-trapping layer comprises silicon-rich nitride may have a refractive index of 2.05 or greater or comprises nano-crystals of germanium (Ge), zirconium oxide (ZrO2), or zinc oxide (ZnO). The thin-film memory transistor may be implemented, for example, in a 3-dimensional array of NOR memory strings formed above a planar surface of a semiconductor substrate.