公开(公告)号：US20190062153A1

公开(公告)日：2019-02-28

申请号：US15688128

申请日：2017-08-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lee-Chuan Tseng ,  Chang-Ming Wu

IPC: B81C1/00 ,  B81B7/02

Abstract: The present disclosure relates to a microelectromechanical systems (MEMS) package featuring a flat plate having a raised edge around its perimeter serving as an anti-stiction device, and an associated method of formation. A CMOS IC is provided having a dielectric structure surrounding a plurality of conductive interconnect layers disposed over a CMOS substrate. A MEMS IC is bonded to the dielectric structure such that it forms a cavity with a lowered central portion the dielectric structure, and the MEMS IC includes a movable mass that is arranged within the cavity. The CMOS IC includes an anti-stiction plate disposed under the movable mass. The anti-stiction plate is made of a conductive material and has a raised edge surrounding at least a part of a perimeter of a substantially planar upper surface.

公开(公告)号：US09917165B2

公开(公告)日：2018-03-13

申请号：US14713462

申请日：2015-05-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L29/788 ,  H01L29/792 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L27/11524 ,  H01L21/8239

CPC classification number: H01L29/42328 ,  H01L21/28273 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/788

Abstract: A split-gate flash memory cell for improved erase speed is provided. An erase gate and a floating gate are laterally spaced over a semiconductor substrate. The floating gate has a height increasing towards the erase gate, a concave sidewall surface neighboring the erase gate, and a tip defined an interface of the concave sidewall surface and an upper surface of the floating gate. A control gate and a sidewall spacer are arranged over the upper surface of the floating gate. The control gate is laterally offset from the tip of the floating gate, and the sidewall spacer is laterally arranged between the control gate and the tip. A method for manufacturing the split-gate flash memory cell is also provided.

公开(公告)号：US20170317095A1

公开(公告)日：2017-11-02

申请号：US15654293

申请日：2017-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Shih-Chang Liu ,  Chia-Shiung Tsai ,  Ru-Liang Lee

IPC: H01L27/11521 ,  H01L29/788 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7881

Abstract: Some embodiments of the present disclosure relate to method of forming a memory device. In some embodiments, the method may be performed by forming a floating gate over a first dielectric on a substrate. A control gate is formed over the floating gate and first and second spacers are formed along sidewalls of the control gate. The first and second spacers extend past outer edges of an upper surface of the floating gate. An etching process is performed on the first and second spacers to remove a portion of the first and second spacers that extends past the outer edges of the upper surface of the floating gate along an interface between the first and second spacers and the floating gate.

公开(公告)号：US09728545B2

公开(公告)日：2017-08-08

申请号：US14688006

申请日：2015-04-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L29/423 ,  H01L21/28 ,  H01L27/105 ,  H01L29/66 ,  H01L29/06 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11519

CPC classification number: H01L27/11548 ,  H01L21/28273 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11526 ,  H01L29/42328 ,  H01L29/66825

Abstract: A method for manufacturing an embedded flash memory device is provided. Memory and logic shallow trench isolation (STI) regions respectively extend into memory and logic regions of a substrate. The memory and logic STI regions have upper surfaces approximately coplanar with an upper surface of a pad layer overlying the substrate. A capping layer is formed overlying the logic region. A first etch is performed into the pad layer to expose memory gaps between the memory STI regions. A floating gate layer is formed filling the memory gaps. A second, dry etch is performed into the floating gate layer to etch the floating gate layer back to below upper surfaces of the capping layer and the memory STI regions. A third etch is performed into the memory STI regions to recess the memory STI regions. A fourth etch is performed into the floating gate layer to form floating gates.

公开(公告)号：US09660188B2

公开(公告)日：2017-05-23

申请号：US14471082

申请日：2014-08-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-ken Lin ,  Chang-Ming Wu ,  Chern-Yow Hsu ,  Shih-Chang Liu

IPC: H01L29/02 ,  H01L47/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/06 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1286 ,  H01L45/1675

Abstract: A phase change memory (PCM) cell with a heating element electrically isolated from laterally surrounding regions of the PCM cell by a cavity is provided. A dielectric region is arranged between first and second conductors. A heating plug is arranged within a hole extending through the dielectric region to the first conductor. The heating plug includes a heating element running along sidewalls of the hole, and includes a sidewall structure including a cavity arranged between the heating element and the sidewalls. A phase change element is in thermal communication with the heating plug and arranged between the heating plug and the second conductor. Also provide is a method for manufacturing the PCM cell.

公开(公告)号：US09583591B2

公开(公告)日：2017-02-28

申请号：US14210796

申请日：2014-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Chin-Yi Huang ,  Shih-Chang Liu ,  Chang-Ming Wu

IPC: H01L21/77 ,  H01L21/336 ,  H01L29/66 ,  H01L27/115

CPC classification number: H01L27/11534 ,  H01L27/11521 ,  H01L29/66545

Abstract: The present disclosure relates to a method of embedding an ESF3 memory in a HKMG integrated circuit that utilizes a replacement gate technology. The ESF3 memory is formed over a recessed substrate which prevents damage of the memory control gates during the CMP process performed on the ILD layer. An asymmetric isolation zone is also formed in the transition region between the memory cell and the periphery circuit boundary.

Abstract translation: 本公开涉及一种在采用替代门技术的HKMG集成电路中嵌入ESF3存储器的方法。 ESF3存储器形成在凹陷的衬底上，防止在ILD层执行的CMP工艺期间对存储器控制栅极的损坏。 在存储单元和外围电路边界之间的过渡区域中也形成非对称隔离区。

公开(公告)号：US09567207B2

公开(公告)日：2017-02-14

申请号：US14713287

申请日：2015-05-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lee-Chuan Tseng ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L29/84 ,  B81B7/00 ,  B81C1/00

CPC classification number: B81B7/0041 ,  B81B7/02 ,  B81B2201/0235 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2207/012 ,  B81C1/00293 ,  B81C2201/0112 ,  B81C2203/0145 ,  B81C2203/019 ,  B81C2203/0785

Abstract: An integrated circuit (IC) device is provided. The IC device includes a first substrate having a frontside and a backside. The backside includes a first cavity extending into the first substrate. A dielectric layer is disposed on the backside of the first substrate, and includes an opening corresponding to the first cavity and a trench extending laterally away from the opening and terminating at a gas inlet recess. A recess in the frontside of the first substrate extends downwardly from the frontside to the dielectric layer. The recess has substantially vertical upper sidewalls which adjoin lower sidewalls which taper inwardly from the substantially vertical sidewalls to points on the dielectric layer which circumscribe the gas inlet recess. A conformal sealant layer is arranged over the frontside of the first substrate, along the substantially vertical upper sidewalls, and along the lower sidewalls. The sealant layer hermetically seals the gas inlet recess.

Abstract translation: 提供集成电路（IC）装置。 IC器件包括具有前侧和后侧的第一基板。 背面包括延伸到第一基底中的第一腔。 电介质层设置在第一基板的背面，并且包括对应于第一空腔的开口和从开口横向延伸并终止于气体入口凹部的沟槽。 第一衬底的前侧的凹部从前侧向下延伸到电介质层。 凹部具有基本上垂直的上侧壁，其邻接下部侧壁，所述下侧壁从基本上垂直的侧壁向内逐渐向包围气体入口凹部的电介质层上的点倾斜。 共形密封剂层沿着基本垂直的上侧壁以及沿着下侧壁设置在第一基板的前侧上。 密封剂层密封气体入口凹部。

公开(公告)号：US09502515B2

公开(公告)日：2016-11-22

申请号：US14980165

申请日：2015-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yuan-Tai Tseng ,  Ming Chyi Liu ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L21/8238 ,  H01L29/792 ,  H01L29/423 ,  H01L29/66 ,  H01L27/115

CPC classification number: H01L29/42344 ,  H01L27/1157 ,  H01L29/66484 ,  H01L29/66833 ,  H01L29/792

Abstract: A method of manufacturing a split gate flash memory cell is provided. A select gate is formed on a semiconductor substrate. A sacrificial spacer is formed laterally adjacent to the select gate and on a first side of the select gate. A charge trapping layer is formed lining upper surfaces of the select gate and the sacrificial spacer, and further lining a sidewall surface of the select gate on a second side of the select gate that is opposite the first side of the select gate. A memory gate is formed over the charge trapping layer and on the second side of the select gate. The sacrificial spacer is removed. The resulting semiconductor structure is also provided.

Abstract translation: 提供了一种制造分离栅闪存单元的方法。 选择栅极形成在半导体衬底上。 牺牲隔离物横向邻近选择栅极并在选择栅极的第一侧上形成。 在选择栅极和牺牲隔离物的上表面上形成电荷捕获层，并且进一步在选择栅极的与选择栅极的第一侧相对的第二侧上衬里选择栅极的侧壁表面。 存储栅极形成在电荷俘获层上和选择栅极的第二侧上。 去除牺牲隔离物。 还提供所得的半导体结构。

公开(公告)号：US20160332867A1

公开(公告)日：2016-11-17

申请号：US14713287

申请日：2015-05-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lee-Chuan Tseng ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/0041 ,  B81B7/02 ,  B81B2201/0235 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2207/012 ,  B81C1/00293 ,  B81C2201/0112 ,  B81C2203/0145 ,  B81C2203/019 ,  B81C2203/0785

Abstract: An integrated circuit (IC) device is provided. The IC device includes a first substrate having a frontside and a backside. The backside includes a first cavity extending into the first substrate. A dielectric layer is disposed on the backside of the first substrate, and includes an opening corresponding to the first cavity and a trench extending laterally away from the opening and terminating at a gas inlet recess. A recess in the frontside of the first substrate extends downwardly from the frontside to the dielectric layer. The recess has substantially vertical upper sidewalls which adjoin lower sidewalls which taper inwardly from the substantially vertical sidewalls to points on the dielectric layer which circumscribe the gas inlet recess. A conformal sealant layer is arranged over the frontside of the first substrate, along the substantially vertical upper sidewalls, and along the lower sidewalls. The sealant layer hermetically seals the gas inlet recess.

Abstract translation: 提供集成电路（IC）装置。 IC器件包括具有前侧和后侧的第一基板。 背面包括延伸到第一基底中的第一腔。 电介质层设置在第一基板的背面，并且包括对应于第一空腔的开口和从开口横向延伸并终止于气体入口凹部的沟槽。 第一衬底的前侧的凹部从前侧向下延伸到电介质层。 凹部具有基本上垂直的上侧壁，其邻接下部侧壁，所述下侧壁从基本上垂直的侧壁向内逐渐向包围气体入口凹部的电介质层上的点倾斜。 共形密封剂层沿着基本垂直的上侧壁以及沿着下侧壁设置在第一基板的前侧上。 密封剂层密封气体入口凹部。

公开(公告)号：US20160307911A1

公开(公告)日：2016-10-20

申请号：US14688006

申请日：2015-04-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L27/115 ,  H01L21/28

CPC classification number: H01L27/11548 ,  H01L21/28273 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11526 ,  H01L29/42328 ,  H01L29/66825

Abstract: A method for manufacturing an embedded flash memory device is provided. Memory and logic shallow trench isolation (STI) regions respectively extend into memory and logic regions of a substrate. The memory and logic STI regions have upper surfaces approximately coplanar with an upper surface of a pad layer overlying the substrate. A capping layer is formed overlying the logic region. A first etch is performed into the pad layer to expose memory gaps between the memory STI regions. A floating gate layer is formed filling the memory gaps. A second, dry etch is performed into the floating gate layer to etch the floating gate layer back to below upper surfaces of the capping layer and the memory STI regions. A third etch is performed into the memory STI regions to recess the memory STI regions. A fourth etch is performed into the floating gate layer to form floating gates.

Abstract translation: 提供一种用于制造嵌入式闪存设备的方法。 存储器和逻辑浅沟槽隔离（STI）区域分别延伸到衬底的存储器和逻辑区域中。 存储器和逻辑STI区域具有与覆盖衬底的衬垫层的上表面大致共面的上表面。 形成覆盖在逻辑区域上的覆盖层。 对焊盘层执行第一蚀刻，以暴露存储器STI区之间的存储器间隙。 形成填充存储器间隙的浮栅层。 执行第二次干法蚀刻到浮栅中以将浮栅蚀刻到覆盖层和存储器STI区的上表面之下。 对存储器STI区域执行第三蚀刻，以凹进存储器STI区域。 执行第四蚀刻到浮栅中以形成浮栅。