公开(公告)号：US11527702B2

公开(公告)日：2022-12-13

申请号：US16108384

申请日：2018-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Chung-Yi Yu

IPC: H01L41/083 ,  H01L41/314 ,  H01L41/047

Abstract: A device includes a substrate, a first layer of getter material, a first electrode, an insulator element, a second electrode, a first input-output electrode, and a second input-output electrode. The first layer of getter material is deposited on the substrate. The first electrode is formed in a first conductive layer deposited on the first layer of getter material. The first layer of getter material has a getter capacity for hydrogen that is higher than the first electrode. The insulator element is formed in a piezoelectric layer deposited on the first electrode. The second electrode is formed in a second conductive layer deposited on the insulator element. The first input-output electrode is conductively connecting to the first layer of getter material. The second input-output electrode is conductively connecting to the second electrode.

公开(公告)号：US11387748B2

公开(公告)日：2022-07-12

申请号：US16801350

申请日：2020-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chiao-Chun Hsu ,  Chih-Ming Chen ,  Chung-Yi Yu ,  Lung Yuan Pan

IPC: H02N1/00

Abstract: In some embodiments, the present disclosure relates to a microelectromechanical system (MEMS) comb actuator including a comb structure. The comb structure includes a support layer having a first material and a plurality of protrusions extending away from a first surface of the support layer in a first direction. The plurality of protrusions are also made of the first material. The plurality of protrusions are separated along a second direction parallel to the first surface of the support layer. The MEMS comb actuator may further include a dielectric liner structure that continuously and completely covers the first surface of the support layer and outer surfaces of the plurality of protrusions. The dielectric liner structure includes a connective portion that continuously connects topmost surfaces of at least two of the plurality of protrusions.

公开(公告)号：US20210126183A1

公开(公告)日：2021-04-29

申请号：US16666395

申请日：2019-10-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen

IPC: H01L41/047 ,  H01L41/083 ,  H01L41/187 ,  H01L41/332 ,  H01L41/316

Abstract: A piezoelectric device including a substrate, a metal-insulator-metal element, a hydrogen blocking layer, a passivation layer, a first contact terminal and a second contact terminal is provided. The metal-insulator-metal element is disposed on the substrate. The hydrogen blocking layer is disposed on the metal-insulator-metal element. The passivation layer covers the hydrogen blocking layer and the metal-insulator-metal element. The first contact terminal is electrically connected to the metal-insulator-metal element. The second contact terminal is electrically connected to the metal-insulator-metal element.

公开(公告)号：US10739671B2

公开(公告)日：2020-08-11

申请号：US15905543

申请日：2018-02-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Chieh Tien ,  Cheng-Hsuen Chiang ,  Chih-Ming Chen ,  Cheng-Ming Lin ,  Yen-Wei Huang ,  Hao-Ming Chang ,  Kuo Chin Lin ,  Kuan-Shien Lee

IPC: G03F1/32 ,  G03F1/38

Abstract: In a method of manufacturing a photo mask, a resist layer is formed over a mask blank, which includes a mask substrate, a phase shift layer disposed on the mask substrate and a light blocking layer disposed on the phase shift layer. A resist pattern is formed by using a lithographic operation. The light blocking layer is patterned by using the resist pattern as an etching mask. The phase shift layer is patterned by using the patterned light blocking layer as an etching mask. A border region of the mask substrate is covered with an etching hard cover, while a pattern region of the mask substrate is opened. The patterned light blocking layer in the pattern region is patterned through the opening of the etching hard cover. A photo-etching operation is performed on the pattern region to remove residues of the light blocking layer.

公开(公告)号：US20200028070A1

公开(公告)日：2020-01-23

申请号：US16587499

申请日：2019-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Chern-Yow Hsu ,  Szu-Yu Wang ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Xiaomeng Chen

IPC: H01L43/08 ,  H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10

Abstract: Some embodiments of the present disclosure relate to a method that achieves a substantially uniform pattern of magnetic random access memory (MRAM) cells with a minimum dimension below the lower resolution limit of some optical lithography techniques. A copolymer solution comprising first and second polymer species is spin-coated over a heterostructure which resides over a surface of a substrate. The heterostructure comprises first and second ferromagnetic layers which are separated by an insulating layer. The copolymer solution is subjected to self-assembly into a phase-separated material comprising a pattern of micro-domains of the second polymer species within a polymer matrix comprising the first polymer species. The first polymer species is then removed, leaving a pattern of micro-domains of the second polymer species. A pattern of magnetic memory cells within the heterostructure is formed by etching through the heterostructure while utilizing the pattern of micro-domains as a hardmask.

公开(公告)号：US20200020845A1

公开(公告)日：2020-01-16

申请号：US16108384

申请日：2018-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Chung-Yi Yu

IPC: H01L41/083 ,  H01L41/047 ,  H01L41/314

Abstract: A device includes a substrate, a first layer of getter material, a first electrode, an insulator element, a second electrode, a first input-output electrode, and a second input-output electrode. The first layer of getter material is deposited on the substrate. The first electrode is formed in a first conductive layer deposited on the first layer of getter material. The first layer of getter material has a getter capacity for hydrogen that is higher than the first electrode. The insulator element is formed in a piezoelectric layer deposited on the first electrode. The second electrode is formed in a second conductive layer deposited on the insulator element. The first input-output electrode is conductively connecting to the first layer of getter material. The second input-output electrode is conductively connecting to the second electrode.

公开(公告)号：US09685518B2

公开(公告)日：2017-06-20

申请号：US14079186

申请日：2013-11-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Ming Chen ,  Chin-Cheng Chang ,  Szu-Yu Wang ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Ru-Liang Lee

IPC: H01L29/51 ,  H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788

CPC classification number: H01L29/42332 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method of forming a semiconductor structure of a control gate is provided, including depositing a first dielectric layer overlying a substrate, forming a surface modification layer from the first dielectric layer; and forming semiconductor dots on the surface modification layer. The surface modification layer has a bonding energy to the semiconductor dots less than the bonding energy between the first dielectric layer and the semiconductor dots. Therefore the semiconductor dots have higher density to form on the surface modification layer than that to directly form on the first dielectric layer. And a semiconductor device is also provided to tighten threshold voltage (Vt) and increase programming efficiency.

公开(公告)号：US09646938B2

公开(公告)日：2017-05-09

申请号：US14881365

申请日：2015-10-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Szu-Yu Wang ,  Chung-Yi Yu

IPC: H01L23/00 ,  H01L21/02 ,  H01L27/108 ,  H01L49/02 ,  H01L21/302 ,  H01L21/822

CPC classification number: H01L23/562 ,  H01L21/02016 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/302 ,  H01L21/30625 ,  H01L21/3205 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/78 ,  H01L21/8221 ,  H01L22/20 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/10829 ,  H01L27/10861 ,  H01L28/40 ,  H01L28/60 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2225/06586 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Wafer bowing induced by deep trench capacitors is ameliorated by structures formed on the reverse side of the wafer. The structures on the reverse side include tensile films. The films can be formed within trenches on the back side of the wafer, which enhances their effect. In some embodiments, the wafers are used to form 3D-IC devices. In some embodiments, the 3D-IC device includes a high voltage or high power circuit.

公开(公告)号：US09577077B2

公开(公告)日：2017-02-21

申请号：US14308808

申请日：2014-06-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsu-Hui Su ,  Chih-Ming Chen ,  Szu-Yu Wang ,  Chung-Yi Yu ,  Chia-Shiung Tsai

IPC: H01L27/115 ,  H01L29/66 ,  H01L29/792 ,  H01L21/28 ,  H01L29/423 ,  H01L29/788

CPC classification number: H01L29/66833 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/792

Abstract: Some embodiments of the present disclosure relate to a method for forming flash memory. In this method, a first tunnel oxide is formed over a semiconductor substrate. A self-assembled monolayer (SAM) is then formed on the first tunnel oxide. The SAM includes spherical or spherical-like crystalline silicon dots having respective diameters which are less than approximately 30 nm. A second tunnel oxide is then formed over the SAM.

Abstract translation: 本公开的一些实施例涉及用于形成快闪存储器的方法。 在该方法中，在半导体衬底上形成第一隧道氧化物。 然后在第一隧道氧化物上形成自组装单层（SAM）。 SAM包括具有小于约30nm的相应直径的球形或球形晶体硅点。 然后在SAM上形成第二隧道氧化物。

公开(公告)号：US09401434B2

公开(公告)日：2016-07-26

申请号：US14489902

申请日：2014-09-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Tsu-Hui Su ,  Szu-Yu Wang ,  Chung-Yi Yu

IPC: H01L29/788 ,  H01L29/792 ,  H01L29/423 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L29/7883 ,  G11C16/0483 ,  G11C16/14 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/0665 ,  H01L29/401 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

Abstract: The present disclosure relates to a structure and method for forming a flash memory cell with an improved erase speed and erase current. Si dots are used for charge trapping and an ONO sandwich structure is formed over the Si dots. Erase operation includes direct tunneling as well as FN tunneling which helps increase erase speed without compensating data retention.

Abstract translation: 本发明涉及用于形成具有改进的擦除速度和擦除电流的闪存单元的结构和方法。 Si点用于电荷俘获，并且在Si点上形成ONO夹层结构。 擦除操作包括直接隧道和FN隧道，这有助于提高擦除速度，而不会补偿数据保留。