公开(公告)号：US11222814B2

公开(公告)日：2022-01-11

申请号：US16600845

申请日：2019-10-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Kuan-Chieh Huang

IPC: H01L21/768 ,  H01L27/088 ,  H01L21/762 ,  H01L23/522 ,  H01L23/48 ,  H01L27/06 ,  H01L21/822 ,  H01L23/525 ,  H01L25/00

Abstract: An integrated circuit (IC) provides high performance and high functional density. A first back-end-of-line (BEOL) interconnect structure and a second BEOL interconnect structure are respectively under and over a semiconductor substrate. A first electronic device and a second electronic device are between the semiconductor substrate and respectively a bottom of the first BEOL interconnect structure and a top of the second BEOL interconnect structure. A through substrate via (TSV) extends through the semiconductor substrate, from the first BEOL interconnect structure to the second BEOL interconnect structure. A method for manufacturing the IC is also provided.

公开(公告)号：US20210280620A1

公开(公告)日：2021-09-09

申请号：US17308332

申请日：2021-05-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Seiji Takahashi ,  Chen-Jong Wang ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Feng-Jia Shiu ,  Jen-Cheng Liu ,  Jhy-Jyi Sze ,  Chun-Wei Chang ,  Wei-Cheng Hsu ,  Wei Chuang Wu ,  Yimin Huang

IPC: H01L27/146

Abstract: In some embodiments, a pixel sensor is provided. The pixel sensor includes a first photodetector arranged in a semiconductor substrate. A second photodetector is arranged in the semiconductor substrate, where a first substantially straight line axis intersects a center point of the first photodetector and a center point of the second photodetector. A floating diffusion node is arranged in the semiconductor substrate at a point that is a substantially equal distance from the first photodetector and the second photodetector. A pick-up well contact region is arranged in the semiconductor substrate, where a second substantially straight line axis that is substantially perpendicular to the first substantially straight line axis intersects a center point of the floating diffusion node and a center point of the pick-up well contact region.

公开(公告)号：US11088196B2

公开(公告)日：2021-08-10

申请号：US16684871

申请日：2019-11-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chiang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Jhy-Jyi Sze ,  Shyh-Fann Ting ,  Yimin Huang

IPC: H01L27/146

Abstract: The problem of reducing noise in image sensing devices, especially NIR detectors, is solved by providing ground connections for the reflectors. The reflectors may be grounded through vias that couple the reflectors to grounded areas of the substrate. The grounded areas of the substrate may be P+ doped areas formed proximate the surface of the substrate. In particular, the P+ doped areas may be parts of photodiodes. Alternatively, the reflectors may be grounded through a metal interconnect structure formed over the front side of the substrate.

公开(公告)号：US20210210534A1

公开(公告)日：2021-07-08

申请号：US16736134

申请日：2020-01-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Ching-Chun Wang ,  Hsiao-Hui Tseng ,  Jen-Cheng Liu ,  Jhy-Jyi Sze ,  Shyh-Fann Ting ,  Wei Chuang Wu ,  Yen-Ting Chiang ,  Chia Ching Liao ,  Yen-Yu Chen

IPC: H01L27/146

Abstract: In some embodiments, the present disclosure relates to a device having a semiconductor substrate including a frontside and a backside. On the frontside of the semiconductor substrate are a first source/drain region and a second source/drain region. A gate electrode is arranged on the frontside of the semiconductor substrate and includes a horizontal portion, a first vertical portion, and a second vertical portion. The horizontal portion is arranged over the frontside of the semiconductor substrate and between the first and second source/drain regions. The first vertical portion extends from the frontside towards the backside of the semiconductor substrate and contacts the horizontal portion of the gate electrode structure. The second vertical portion extends from the frontside towards the backside of the semiconductor substrate, contacts the horizontal portion of the gate electrode structure, and is separated from the first vertical portion by a channel region of the substrate.

公开(公告)号：US11043522B2

公开(公告)日：2021-06-22

申请号：US16167810

申请日：2018-10-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jeng-Shyan Lin ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Hsun-Ying Huang ,  Wei-Chih Weng ,  Yu-Yang Shen

IPC: H01L27/146 ,  H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L21/78 ,  H01L23/528 ,  H01L25/065 ,  H01L25/00 ,  H01L23/532

Abstract: The present disclosure, in some embodiments, relates to a multi-dimensional integrated chip structure. The structure includes a first interconnect layer within a first dielectric structure on a first substrate, and a second interconnect layer within a second dielectric structure on a second substrate. A bonding structure is between the first dielectric structure and the second substrate. An inter-tier interconnect structure extends through the second substrate and between a top of the first interconnect layer and a bottom of the second interconnect layer. The inter-tier interconnect structure includes a first region having substantially vertical sidewalls extending through the second substrate and a second region below the first region and having tapered sidewalls surrounded by the bonding structure.

公开(公告)号：US20210159264A1

公开(公告)日：2021-05-27

申请号：US17166387

申请日：2021-02-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Pao-Tung Chen ,  Dun-Nian Yaung ,  Jen-Cheng Liu

IPC: H01L27/146 ,  H01L23/498 ,  H01L21/768

Abstract: Methods for forming via last through-vias. A method includes providing an active device wafer having a front side including conductive interconnect material disposed in dielectric layers and having an opposing back side; providing a carrier wafer having through vias filled with an oxide extending from a first surface of the carrier wafer to a second surface of the carrier wafer; bonding the front side of the active device wafer to the second surface of the carrier wafer; etching the oxide in the through vias in the carrier wafer to form through oxide vias; and depositing conductor material into the through oxide vias to form conductors that extend to the active carrier wafer and make electrical contact to the conductive interconnect material. An apparatus includes a carrier wafer with through oxide vias extending through the carrier wafer to an active device wafer bonded to the carrier wafer.

公开(公告)号：US10964692B2

公开(公告)日：2021-03-30

申请号：US16578299

申请日：2019-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kong-Beng Thei ,  Dun-Nian Yaung ,  Fu-Jier Fan ,  Hsing-Chih Lin ,  Hsiao-Chin Tuan ,  Jen-Cheng Liu ,  Alexander Kalnitsky ,  Yi-Sheng Chen

IPC: H01L21/00 ,  H01L27/06 ,  H01L23/48 ,  H01L23/00 ,  H01L23/522 ,  H01L23/31 ,  H01L21/48

Abstract: A three-dimensional (3D) integrated circuit (IC) and associated forming method are provided. In some embodiments, a second IC die is bonded to a first IC die through a second bonding structure and a first bonding structure at a bonding interface. The bonding encloses a seal-ring structure in a peripheral region of the 3D IC in the first and second IC dies. The seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate. The bonding forms a plurality of through silicon via (TSV) coupling structures at the peripheral region of the 3D IC along an inner perimeter of the seal-ring structure by electrically and correspondingly connects a first plurality of TSV wiring layers and inter-wire vias and a second plurality of TSV wiring layers and inter-wire vias.

公开(公告)号：US10790327B2

公开(公告)日：2020-09-29

申请号：US16861453

申请日：2020-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Hsun-Ying Huang

IPC: H01L21/00 ,  H01L27/146 ,  H01L23/48

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor die, and a second semiconductor die bonded on the first semiconductor die. A through-substrate via penetrates through a semiconductor substrate of the second semiconductor die. A passivation layer is disposed between the first semiconductor die and the second semiconductor die, wherein the passivation layer is directly bonded to the semiconductor substrate of the second semiconductor die. A conductive feature passes through the passivation layer, wherein the conductive feature is bonded to the through-substrate via. A barrier layer is disposed between the conductive feature and the passivation layer. The barrier layer covers sidewalls of the conductive feature and separates the surface of the conductive feature from a nearest neighboring surface of the first or second semiconductor die.

公开(公告)号：US10790194B2

公开(公告)日：2020-09-29

申请号：US16584809

申请日：2019-09-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Han Huang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Min-Feng Kao

IPC: H01L21/822 ,  H01L23/522 ,  H01L23/00 ,  H01L25/065 ,  H01L27/06 ,  H01F17/00 ,  H01F41/04 ,  H01L21/768 ,  H01L27/08 ,  H01L49/02

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first plurality of conductive interconnect layers arranged within a first inter-level dielectric (ILD) structure disposed on a first surface of a first substrate. A second plurality of conductive interconnect layers are arranged within a second ILD structure disposed on a first surface of a second substrate. The second substrate is separated from the first substrate by the first ILD structure. The first plurality of conductive interconnect layers and the second plurality of conductive interconnect layers define an inductor having one or more turns.

公开(公告)号：US20200303351A1

公开(公告)日：2020-09-24

申请号：US16896348

申请日：2020-06-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ming Wu ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Min-Feng Kao ,  Yung-Lung Lin ,  Shih-Han Huang ,  I-Nan Chen

IPC: H01L25/065 ,  H01L23/528 ,  H01L23/48 ,  H01L25/00 ,  H01L23/00 ,  H01L23/532

Abstract: A method for manufacturing three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is formed and bonded to a first IC die by a first bonding structure. A third IC die is formed and bonded to the second IC die by a second bonding structure. The second bonding structure is formed between back sides of the second IC die and the third IC die opposite to corresponding interconnect structures and comprises a first TSV (through substrate via) disposed through a second substrate of the second IC die and a second TSV disposed through a third substrate of the third IC die. In some further embodiments, the second bonding structure is formed by forming conductive features with oppositely titled sidewalls disposed between the first TSV and the second TSV.