公开(公告)号：US12074057B2

公开(公告)日：2024-08-27

申请号：US18057688

申请日：2022-11-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Kuo-Hua Pan ,  Jhon Jhy Liaw

IPC: H01L21/762 ,  G06F30/392 ,  H01L21/84 ,  H01L29/06

CPC classification number: H01L21/76283 ,  H01L21/845 ,  H01L29/0649 ,  G06F30/392

Abstract: Semiconductor structures and methods are provided. A semiconductor structure according to an embodiment includes a first cell disposed over a first well doped with a first-type dopant, a second cell disposed over the first well, and a tap cell disposed over the first well. The tap cell is sandwiched between the first cell and the second cell. The first cell includes a first plurality of transistors and the second cell includes a second plurality of transistors.

公开(公告)号：US20240266167A1

公开(公告)日：2024-08-08

申请号：US18594463

申请日：2024-03-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Che Chiang ,  Wei-Chih Kao ,  Chun-Sheng Liang ,  Kuo-Hua Pan

IPC: H01L21/02 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/0245 ,  H01L21/02507 ,  H01L21/02587 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a semiconductor substrate having a first lattice constant, a fin-shape base protruding from the semiconductor substrate and extending lengthwise in a first direction, nanostructures suspended above the fin-shape base, a metal gate structure wrapping around each of the nanostructures, an epitaxial feature abutting the nanostructures, and inner spacers interposing the epitaxial feature and the metal gate structure. In a cross section perpendicular to the first direction the fin-shape base includes a first layer and a second layer over the first layer. The first layer has a second lattice constant different from the first lattice constant, and the second layer has a third lattice constant different from the second lattice constant. A portion of the metal gate structure is sandwiched between the second layer and a bottommost one of the nanostructures.

公开(公告)号：US12057485B2

公开(公告)日：2024-08-06

申请号：US17409086

申请日：2021-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shien-Yang Wu ,  Ta-Chun Lin ,  Kuo-Hua Pan

IPC: H01L29/423 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/165 ,  H01L29/40 ,  H01L29/66 ,  H01L21/027

CPC classification number: H01L29/42392 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/401 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/0274

Abstract: A method of manufacturing a device includes forming a plurality of stacks of alternating layers on a substrate, constructing a plurality of nanosheets from the plurality of stacks of alternating layers, and forming a plurality of gate dielectrics over the plurality of nanosheets, respectively. The method allows for the modulation of nanosheet width, thickness, spacing, and stack number and can be employed on single substrates. This design flexibility provides for design optimization over a wide tuning range of circuit performance and power usage.

公开(公告)号：US11742349B2

公开(公告)日：2023-08-29

申请号：US17717296

申请日：2022-04-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Kuo-Hua Pan ,  Jhon Jhy Liaw ,  Shien-Yang Wu

IPC: H01L21/00 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823462 ,  H01L29/0673 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes forming a first channel region, a second channel region, and a third channel region over a substrate, depositing a first interfacial layer over the first, second, and third channel regions, removing the first interfacial layer from the first and second channel regions, depositing a second interfacial layer over the first and second channel regions, thinning a thickness of the second interfacial layer over the first channel region, depositing a high-k dielectric layer over the first, second, and third channel regions, and forming a gate electrode layer over the first, second, and third channel regions.

公开(公告)号：US11721763B2

公开(公告)日：2023-08-08

申请号：US17124994

申请日：2020-12-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wen-Che Tsai ,  Min-Yann Hsieh ,  Hua-Feng Chen ,  Kuo-Hua Pan

IPC: H01L29/78 ,  H01L21/768 ,  H01L29/66 ,  H01L29/417 ,  H01L23/522 ,  H01L23/528 ,  H01L29/165 ,  H01L23/485

CPC classification number: H01L29/7851 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/5283 ,  H01L29/41766 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L23/485 ,  H01L29/165 ,  H01L29/7848 ,  H01L2029/7858

Abstract: A method comprises forming a source/drain region on a substrate; forming a dielectric layer over the source/drain region; forming a contact hole in the dielectric layer; forming a contact hole liner in the contact hole; removing a first portion of the contact hole liner to expose a sidewall of the contact hole; etching the exposed sidewall of the contact hole to laterally expand the contact hole; and forming a contact plug in the laterally expanded contact hole.

公开(公告)号：US11688791B2

公开(公告)日：2023-06-27

申请号：US16680816

申请日：2019-11-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Jhon Jhy Liaw ,  Kuo-Hua Pan

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/762 ,  H01L21/308 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/786 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/76831 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696

Abstract: A semiconductor structure includes a first active region over a substrate and extending along a first direction, a gate structure over the first active region and extending along a second direction substantially perpendicular to the first direction, a gate-cut feature abutting an end of the gate structure, and a channel isolation feature extending along the second direction and between the first active region and a second active region. The gate structure includes a metal electrode in direct contact with the gate-cut feature. The channel isolation feature includes a liner on sidewalls extending along the second direction and a dielectric fill layer between the sidewalls. The gate-cut feature abuts an end of the channel isolation feature and the dielectric fill layer is in direct contact with the gate-cut feature.

公开(公告)号：US20230081710A1

公开(公告)日：2023-03-16

申请号：US18057688

申请日：2022-11-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Kuo-Hua Pan ,  Jhon Jhy Liaw

IPC: H01L21/762 ,  H01L21/84 ,  H01L29/06

Abstract: Semiconductor structures and methods are provided. A semiconductor structure according to an embodiment includes a first cell disposed over a first well doped with a first-type dopant, a second cell disposed over the first well, and a tap cell disposed over the first well. The tap cell is sandwiched between the first cell and the second cell. The first cell includes a first plurality of transistors and the second cell includes a second plurality of transistors.

公开(公告)号：US11374006B2

公开(公告)日：2022-06-28

申请号：US16899592

申请日：2020-06-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-San Chien ,  Chun-Sheng Liang ,  Jhon-Jhy Liaw ,  Kuo-Hua Pan ,  Hsin-Che Chiang

IPC: H01L27/092 ,  H01L21/8238

Abstract: Provided are a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a plurality of hybrid fins, a gate, and a dielectric structure. The substrate includes a plurality of fins. The plurality of hybrid fins are respectively disposed between the plurality of fins. The gate covers portions of the plurality of fins and the plurality of hybrid fins. The dielectric structure lands on one of the plurality of hybrid fins to divide the gate into two segment. The two segments are electrically isolated to each other by the dielectric structure and the one of the plurality of hybrid fins.

公开(公告)号：US20210408000A1

公开(公告)日：2021-12-30

申请号：US16917778

申请日：2020-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Kuan-Lin Yeh ,  Chun-Jun Lin ,  Kuo-Hua Pan ,  Mu-Chi Chiang

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/768

Abstract: A semiconductor device includes a first active region and a second active region disposed over a substrate. A first source/drain component is grown on the first active region. A second source/drain component is grown on the second active region. An interlayer dielectric (ILD) is disposed around the first source/drain component and the second source/drain component. An isolation structure extends vertically through the ILD. The isolation structure separates the first source/drain component from the second source/drain component.

公开(公告)号：US11101385B2

公开(公告)日：2021-08-24

申请号：US16135108

申请日：2018-09-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Li Chiu ,  Hsin-Che Chiang ,  Chun-Sheng Liang ,  Kuo-Hua Pan

IPC: H01L29/66 ,  H01L21/768 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/033

Abstract: A method for forming a FinFET device structure is provided. The method for forming a FinFET device structure includes forming a fin structure over a substrate and forming a gate structure across the fin structure. The method for forming a FinFET device structure also includes forming a first spacer over a sidewall of the gate structure and forming a second spacer over the first spacer. The method for forming a FinFET device structure further includes etching the second spacer to form a gap and forming a mask layer over the gate structure and the first spacer after the gap is formed. In addition, the mask layer extends into the gap in such a way that the mask layer and the fin structure are separated by an air gap in the gap.