公开(公告)号：US20150372034A1

公开(公告)日：2015-12-24

申请号：US14308910

申请日：2014-06-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chau Chen ,  Chih-Yu Lai ,  Kuo-Ming Wu ,  Kuo-Hwa Tzeng ,  Cheng-Hsien Chou ,  Cheng-Yuan Tsai ,  Yeur-Luen Tu ,  Chia-Shiung Tsai

IPC: H01L27/146 ,  H01L29/423 ,  H01L21/308 ,  H01L29/66 ,  H01L21/306 ,  H01L29/51 ,  H01L21/02

CPC classification number: H01L27/14614 ,  H01L27/1463 ,  H01L27/14643 ,  H01L27/14689 ,  H01L29/4236 ,  H01L29/517 ,  H01L29/66621

Abstract: A vertical-gate transfer transistor of an active pixel sensor (APS) is provided. The transistor includes a semiconductor substrate, a vertical trench extending into the semiconductor substrate, a dielectric lining the vertical trench, and a vertical gate filling the lined vertical trench. The dielectric includes a dielectric constant exceeding 3.9 (i.e., the dielectric constant of silicon dioxide). A method of manufacturing the vertical-gate transfer transistor, an APS including the vertical-gate transfer transistor, a method of manufacturing the APS, and an image sensor including a plurality of the APSs are also provided.

Abstract translation: 提供了一种有源像素传感器（APS）的垂直栅极传输晶体管。 晶体管包括半导体衬底，延伸到半导体衬底中的垂直沟槽，垂直沟槽的电介质衬里，以及填充衬里垂直沟槽的垂直栅极。 电介质包括超过3.9的介电常数（即二氧化硅的介电常数）。 还提供了制造垂直栅极转移晶体管的方法，包括垂直栅极转移晶体管的APS，制造APS的方法以及包括多个APS的图像传感器。

公开(公告)号：US20140264588A1

公开(公告)日：2014-09-18

申请号：US13863697

申请日：2013-04-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.

Inventor： Po-Yu Chen ,  Wan-Hua Huang ,  Kuo-Ming Wu

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/512 ,  H01L29/513 ,  H01L29/6656 ,  H01L29/66689 ,  H01L29/7833 ,  H01L29/7835

Abstract: The present disclosure relates to a method of ultra-high voltage UHV device formation which utilizes a composite step oxide as a gate oxide to achieve isolation of the gate and drain-side spacer from the drain region. The thickness of the step gate oxide improves device breakdown voltage, and allows for the drain to be self-aligned to the gate, thus reducing device drift region and improves device on state resistance. The composite isolation layer comprises two or more dielectric layers which are formed through a series of deposition and etch steps including thermal oxidation and chemical vapor deposition. The composite isolation layer may then be etched to form a self-align structure which utilizes the spacers as hard mask to achieve a reduced device pitch relative to some prior art methods. A thicker gate oxide under one or both spacers can improve yield and high temperature operating life of the UHV device.

Abstract translation: 本公开涉及一种利用复合步进氧化物作为栅极氧化物以实现栅极和漏极侧隔离物与漏极区隔离的超高压特高压器件形成方法。 步进栅极氧化物的厚度提高了器件击穿电压，并允许漏极与栅极自对准，从而减少器件漂移区域，并提高器件导通状态电阻。 复合隔离层包括通过包括热氧化和化学气相沉积在内的一系列沉积和蚀刻步骤形成的两个或多个电介质层。 然后可以蚀刻复合隔离层以形成自对准结构，其利用间隔物作为硬掩模以相对于一些现有技术方法实现减小的器件间距。 在一个或两个间隔物下面较厚的栅极氧化物可以提高UHV器件的产量和高温工作寿命。

公开(公告)号：US20240379462A1

公开(公告)日：2024-11-14

申请号：US18779481

申请日：2024-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hong-Shyang Wu ,  Kuo-Ming Wu

IPC: H01L21/8258 ,  H01L21/762 ,  H01L21/768 ,  H01L21/84 ,  H01L23/535 ,  H01L27/12

Abstract: In an embodiment, a device includes: a gallium nitride device on a substrate, the gallium nitride device including an electrode; a dielectric layer on and around the gallium nitride device; an isolation layer on the dielectric layer; a semiconductor layer on the isolation layer, the semiconductor layer including a silicon device; a through via extending through the semiconductor layer, the isolation layer, and the dielectric layer, the through via electrically and physically coupled to the electrode of the gallium nitride device; and an interconnect structure on the semiconductor layer, the interconnect structure including metallization patterns electrically coupled to the through via and the silicon device.

公开(公告)号：US11951569B2

公开(公告)日：2024-04-09

申请号：US17317977

申请日：2021-05-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ming Wu ,  Yung-Lung Lin ,  Hau-Yi Hsiao ,  Sheng-Chau Chen ,  Cheng-Yuan Tsai

IPC: H01L21/02 ,  B23K26/035 ,  B23K26/062 ,  B23K26/361 ,  H01L21/66

CPC classification number: B23K26/361 ,  B23K26/035 ,  B23K26/062 ,  H01L21/02021 ,  H01L22/10

Abstract: In some embodiments, the present disclosure relates to a wafer edge trimming apparatus that includes a processing chamber defined by chamber housing. Within the processing chamber is a wafer chuck configured to hold onto a wafer structure. Further, a blade is arranged near an edge of the wafer chuck and configured to remove an edge potion of the wafer structure and to define a new sidewall of the wafer structure. A laser sensor apparatus is configured to direct a laser beam directed toward a top surface of the wafer chuck. The laser sensor apparatus is configured to measure a parameter of an analysis area of the wafer structure. Control circuitry is to the laser sensor apparatus and the blade. The control circuitry is configured to start a damage prevention process when the parameter deviates from a predetermined threshold value by at least a predetermined shift value.

公开(公告)号：US20230154898A1

公开(公告)日：2023-05-18

申请号：US18156848

申请日：2023-01-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ming Wu ,  Yung-Lung Lin ,  Zhi-Yang Wang ,  Sheng-Chau Chen ,  Cheng-Hsien Chou

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L24/06 ,  H01L24/02

Abstract: A structure and a method of forming are provided. The structure includes a first dielectric layer overlying a first substrate. A first connection pad is disposed in a top surface of the first dielectric layer and contacts a first redistribution line. A first dummy pad is disposed in the top surface of the first dielectric layer, the first dummy pad contacting the first redistribution line. A second dielectric layer overlies a second substrate. A second connection pad and a second dummy pad are disposed in the top surface of the second dielectric layer, the second connection pad bonded to the first connection pad, and the first dummy pad positioned in a manner that is offset from the second dummy pad so that the first dummy pad and the second dummy pad do not contact each other.

公开(公告)号：US11424359B2

公开(公告)日：2022-08-23

申请号：US17142618

申请日：2021-01-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Chou Lin ,  Yi-Cheng Chiu ,  Karthick Murukesan ,  Yi-Min Chen ,  Shiuan-Jeng Lin ,  Wen-Chih Chiang ,  Chen-Chien Chang ,  Chih-Yuan Chan ,  Kuo-Ming Wu ,  Chun-Lin Tsai

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/40 ,  H01L29/06 ,  H01L29/423

Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.

公开(公告)号：US11189583B2

公开(公告)日：2021-11-30

申请号：US16723041

申请日：2019-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chau Chen ,  Shih-Pei Chou ,  Ming-Che Lee ,  Kuo-Ming Wu ,  Cheng-Hsien Chou ,  Cheng-Yuan Tsai ,  Yeur-Luen Tu

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/768

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure comprises a semiconductive substrate and an interconnect structure over the semiconductive substrate. The semiconductor structure also comprises a bond pad in the semiconductive substrate and coupled to the metal layer. The bond pad comprises two conductive layers.

公开(公告)号：US11127635B1

公开(公告)日：2021-09-21

申请号：US16866685

申请日：2020-05-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Lung Lin ,  Cheng-Hsien Chou ,  Cheng-Yuan Tsai ,  Kuo-Ming Wu ,  Hau-Yi Hsiao

IPC: H01L21/822 ,  H01L21/304 ,  H01L29/06 ,  H01L27/06

Abstract: The present disclosure relates to a method for forming a multi-dimensional integrated chip structure. In some embodiments, the method may be performed by bonding a second substrate to an upper surface of a first substrate. A first edge trimming cut is performed along a first loop and extends into a first peripheral portion of the second substrate. A second edge trimming cut is performed along a second loop and extends into a second peripheral portion of the second substrate and into the first substrate. A third edge trimming cut is performed along a third loop and extends into a third peripheral portion of the first substrate.

公开(公告)号：US10964781B2

公开(公告)日：2021-03-30

申请号：US16199483

申请日：2018-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Cheng Chiu ,  Wen-Chih Chiang ,  Chun Lin Tsai ,  Kuo-Ming Wu ,  Shiuan-Jeng Lin ,  Yi-Min Chen ,  Hung-Chou Lin ,  Karthick Murukesan

IPC: H01L29/06 ,  H01L29/10 ,  H01L23/528 ,  H01L23/522 ,  H01L29/78 ,  H01L29/66 ,  H01L29/8605

Abstract: The present disclosure, in some embodiments, relates to a high voltage resistor device. The device includes a buried well region disposed within a substrate and having a first doping type. A drift region is disposed within the substrate and contacts the buried well region. The drift region has the first doping type. A body region is disposed within the substrate and has a second doping type. The body region laterally contacts the drift region and vertically contacts the buried well region. An isolation structure is over the drift region and a resistor structure is over the isolation structure.

公开(公告)号：US20200350302A1

公开(公告)日：2020-11-05

申请号：US16933082

申请日：2020-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ming Wu ,  Kuan-Liang Liu ,  Wen-De Wang ,  Yung-Lung Lin

IPC: H01L25/00 ,  H01L23/58 ,  H01L23/00

Abstract: Some embodiments relate to a three-dimensional (3D) integrated circuit (IC). The 3D IC includes a first IC die comprising a first semiconductor substrate, and a first interconnect structure over the first semiconductor substrate. The 3D IC also includes a second IC die comprising a second semiconductor substrate, and a second interconnect structure that separates the second semiconductor substrate from the first interconnect structure. A seal ring structure separates the first interconnect structure from the second interconnect structure and perimetrically surrounds a gas reservoir between the first IC die and second IC die. The seal ring structure includes a sidewall gas-vent opening structure configured to allow gas to pass between the gas reservoir and an ambient environment surrounding the 3D IC.